mirror of
https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-19 07:11:28 +03:00
add testbench
This commit is contained in:
UzixLS
14
.gitignore
vendored
14
.gitignore
vendored
@ -27,13 +27,13 @@ fpga/**/simulation/
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fpga.*/
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## Testbench
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fpga_tb/ivl_vhdl_work/
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fpga_tb/work/
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fpga_tb/*.gtkw
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fpga_tb/*.vcd
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fpga_tb/*.bin
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fpga_tb/*.mem
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fpga_tb.*/
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fpga/tb/ivl_vhdl_work/
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fpga/tb/work/
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fpga/tb/*.gtkw
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fpga/tb/*.vcd
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fpga/tb/*.bin
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fpga/tb/*.mem
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fpga/tb.*/
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## Etc.
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*.bak
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@ -20,11 +20,11 @@ module cpucontrol(
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input ext_wait_cycle,
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input init_done_in,
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output n_rstcpu,
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output clkcpu,
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output reg n_rstcpu,
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output reg clkcpu,
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output clkcpu_ck,
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output clkwait,
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output n_int,
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output reg n_int,
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output n_int_next,
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output snow
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);
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@ -47,7 +47,7 @@ assign snow = (timings != TIMINGS_PENT) && bus.a[14] && ~bus.a[15] && bus.rfsh;
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/* CLOCK */
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logic [2:0] turbo_wait;
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wire turbo_wait_trig0 = bus.rd || bus.wr;
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wire turbo_wait_trig1;
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reg turbo_wait_trig1;
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always @(posedge clk28) begin
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turbo_wait_trig1 <= turbo_wait_trig0;
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turbo_wait[0] <= turbo == TURBO_14 && turbo_wait_trig0 && !turbo_wait_trig1;
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139
fpga/rtl/ps2.v
139
fpga/rtl/ps2.v
@ -12,7 +12,7 @@ module ps2#(
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output ps2_dat_out,
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input [7:0] zxkb_addr,
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output [4:0] zxkb_data,
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output reg [4:0] zxkb_data,
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output reg key_magic,
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output reg key_reset,
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output reg key_pause,
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@ -56,89 +56,84 @@ always @(posedge clk or negedge rst_n) begin
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is_ext <= 0;
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key_magic <= 0;
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key_pause <= 0;
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key2_alt <= 0;
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key2_del <= 0;
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joy_up <= 0;
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joy_down <= 0;
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joy_left <= 0;
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joy_right <= 0;
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joy_fire <= 0;
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{joy_up, joy_down, joy_left, joy_right, joy_fire} <= 0;
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{key2_a, key2_b, key2_c, key2_d, key2_e, key2_f, key2_g, key2_h, key2_i, key2_j, key2_k, key2_l, key2_m, key2_n} <= 0;
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{key2_o, key2_p, key2_q, key2_r, key2_s, key2_t, key2_u, key2_v, key2_w, key2_x, key2_y, key2_z, key2_0, key2_1} <= 0;
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{key2_2, key2_3, key2_4, key2_5, key2_6, key2_7, key2_8, key2_9, key2_space, key2_enter, key2_l_shift, key2_r_shift} <= 0;
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{key2_l_ctrl, key2_r_ctrl, key2_up, key2_down, key2_left, key2_right, key2_esc, key2_backspace, key2_accent} <= 0;
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{key2_minus, key2_equals, key2_back_slash, key2_tab, key2_l_bracket, key2_r_bracket, key2_semicolon, key2_quote} <= 0;
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{key2_comma, key2_period, key2_slash, key2_caps, key2_pgup, key2_pgdn} <= 0;
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{key2_alt, key2_del} <= 0;
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end
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else begin
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if (rxdone) begin
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case ({is_ext, rxbyte})
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`PS2_A: key2_a = is_press;
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`PS2_B: key2_b = is_press;
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`PS2_C: key2_c = is_press;
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`PS2_D: key2_d = is_press;
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`PS2_E: key2_e = is_press;
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`PS2_F: key2_f = is_press;
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`PS2_G: key2_g = is_press;
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`PS2_H: key2_h = is_press;
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`PS2_I: key2_i = is_press;
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`PS2_J: key2_j = is_press;
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`PS2_K: key2_k = is_press;
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`PS2_L: key2_l = is_press;
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`PS2_M: key2_m = is_press;
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`PS2_N: key2_n = is_press;
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`PS2_O: key2_o = is_press;
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`PS2_P: key2_p = is_press;
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`PS2_Q: key2_q = is_press;
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`PS2_R: key2_r = is_press;
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`PS2_S: key2_s = is_press;
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`PS2_T: key2_t = is_press;
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`PS2_U: key2_u = is_press;
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`PS2_V: key2_v = is_press;
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`PS2_W: key2_w = is_press;
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`PS2_X: key2_x = is_press;
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`PS2_Y: key2_y = is_press;
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`PS2_Z: key2_z = is_press;
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`PS2_0: key2_0 = is_press;
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`PS2_1: key2_1 = is_press;
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`PS2_2: key2_2 = is_press;
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`PS2_3: key2_3 = is_press;
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`PS2_4: key2_4 = is_press;
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`PS2_5: key2_5 = is_press;
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`PS2_6: key2_6 = is_press;
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`PS2_7: key2_7 = is_press;
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`PS2_8: key2_8 = is_press;
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`PS2_9: key2_9 = is_press;
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`PS2_SPACE: key2_space = is_press;
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`PS2_ENTER: key2_enter = is_press;
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`PS2_A: key2_a <= is_press;
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`PS2_B: key2_b <= is_press;
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`PS2_C: key2_c <= is_press;
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`PS2_D: key2_d <= is_press;
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`PS2_E: key2_e <= is_press;
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`PS2_F: key2_f <= is_press;
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`PS2_G: key2_g <= is_press;
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`PS2_H: key2_h <= is_press;
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`PS2_I: key2_i <= is_press;
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`PS2_J: key2_j <= is_press;
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`PS2_K: key2_k <= is_press;
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`PS2_L: key2_l <= is_press;
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`PS2_M: key2_m <= is_press;
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`PS2_N: key2_n <= is_press;
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`PS2_O: key2_o <= is_press;
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`PS2_P: key2_p <= is_press;
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`PS2_Q: key2_q <= is_press;
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`PS2_R: key2_r <= is_press;
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`PS2_S: key2_s <= is_press;
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`PS2_T: key2_t <= is_press;
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`PS2_U: key2_u <= is_press;
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`PS2_V: key2_v <= is_press;
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`PS2_W: key2_w <= is_press;
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`PS2_X: key2_x <= is_press;
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`PS2_Y: key2_y <= is_press;
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`PS2_Z: key2_z <= is_press;
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`PS2_0: key2_0 <= is_press;
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`PS2_1: key2_1 <= is_press;
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`PS2_2: key2_2 <= is_press;
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`PS2_3: key2_3 <= is_press;
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`PS2_4: key2_4 <= is_press;
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`PS2_5: key2_5 <= is_press;
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`PS2_6: key2_6 <= is_press;
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`PS2_7: key2_7 <= is_press;
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`PS2_8: key2_8 <= is_press;
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`PS2_9: key2_9 <= is_press;
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`PS2_SPACE: key2_space <= is_press;
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`PS2_ENTER: key2_enter <= is_press;
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`PS2_L_SHIFT: key2_l_shift = is_press;
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`PS2_R_SHIFT: key2_r_shift = is_press;
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`PS2_L_CTRL: key2_l_ctrl = is_press;
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`PS2_R_CTRL: key2_r_ctrl = is_press;
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`PS2_L_SHIFT: key2_l_shift <= is_press;
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`PS2_R_SHIFT: key2_r_shift <= is_press;
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`PS2_L_CTRL: key2_l_ctrl <= is_press;
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`PS2_R_CTRL: key2_r_ctrl <= is_press;
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`PS2_UP: key2_up = is_press;
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`PS2_DOWN: key2_down = is_press;
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`PS2_LEFT: key2_left = is_press;
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`PS2_RIGHT: key2_right = is_press;
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`PS2_UP: key2_up <= is_press;
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`PS2_DOWN: key2_down <= is_press;
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`PS2_LEFT: key2_left <= is_press;
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`PS2_RIGHT: key2_right <= is_press;
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`PS2_ESC: key2_esc = is_press;
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`PS2_BACKSPACE: key2_backspace = is_press;
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`PS2_ACCENT: key2_accent = is_press;
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`PS2_MINUS: key2_minus = is_press;
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`PS2_EQUALS: key2_equals = is_press;
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`PS2_BACK_SLASH: key2_back_slash = is_press;
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`PS2_TAB: key2_tab = is_press;
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`PS2_L_BRACKET: key2_l_bracket = is_press;
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`PS2_R_BRACKET: key2_r_bracket = is_press;
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`PS2_SEMICOLON: key2_semicolon = is_press;
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`PS2_QUOTE: key2_quote = is_press;
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`PS2_COMMA: key2_comma = is_press;
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`PS2_PERIOD: key2_period = is_press;
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`PS2_SLASH: key2_slash = is_press;
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`PS2_CAPS: key2_caps = is_press;
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`PS2_PGUP: key2_pgup = is_press;
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`PS2_PGDN: key2_pgdn = is_press;
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`PS2_ESC: key2_esc <= is_press;
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`PS2_BACKSPACE: key2_backspace <= is_press;
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`PS2_ACCENT: key2_accent <= is_press;
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`PS2_MINUS: key2_minus <= is_press;
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`PS2_EQUALS: key2_equals <= is_press;
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`PS2_BACK_SLASH: key2_back_slash <= is_press;
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`PS2_TAB: key2_tab <= is_press;
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`PS2_L_BRACKET: key2_l_bracket <= is_press;
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`PS2_R_BRACKET: key2_r_bracket <= is_press;
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`PS2_SEMICOLON: key2_semicolon <= is_press;
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`PS2_QUOTE: key2_quote <= is_press;
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`PS2_COMMA: key2_comma <= is_press;
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`PS2_PERIOD: key2_period <= is_press;
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`PS2_SLASH: key2_slash <= is_press;
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`PS2_CAPS: key2_caps <= is_press;
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`PS2_PGUP: key2_pgup <= is_press;
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`PS2_PGDN: key2_pgdn <= is_press;
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`PS2_F5: key_magic <= is_press;
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`PS2_F11: key_pause <= 1'b0;
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@ -211,7 +206,7 @@ wire key_8 = key2_8 | key2_right | key2_l_bracket;
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wire key_9 = key2_9 | key2_r_bracket;
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wire key_en = key2_enter;
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wire key_sp = key2_space | key2_esc;
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wire key_cs = key2_l_shift | key2_r_shift | key2_up | key2_down | key2_left | key2_right | key2_esc | key2_backspace |
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wire key_cs = key2_l_shift | key2_r_shift | key2_up | key2_down | key2_left | key2_right | key2_esc | key2_backspace
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| key2_tab | key2_caps | key2_pgup | key2_pgdn ;
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wire key_ss = key2_l_ctrl | key2_r_ctrl | key2_accent | key2_minus | key2_equals | key2_back_slash | key2_l_bracket
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| key2_r_bracket | key2_semicolon | key2_quote | key2_comma | key2_period | key2_slash ;
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@ -20,6 +20,7 @@ localparam CLKWAIT_TICKS = int'(CLKWAIT_US*CLK_FREQ/1e6) + 1'b1;
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localparam TOUT_US = 100; // must be greater than CLKWAIT_US
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localparam TOUT_TICKS = int'(TOUT_US*CLK_FREQ/1e6) + 1'b1;
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localparam TIMER_WIDTH = $clog2(TOUT_TICKS);
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reg [TIMER_WIDTH-1:0] timer;
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reg ps2_freeze; // debounce
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@ -43,7 +44,6 @@ always @(posedge clk or negedge rst_n) begin
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end
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reg [TIMER_WIDTH-1:0] timer;
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reg [3:0] bit_cnt;
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reg [9:0] rxbits;
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assign dataout = rxbits[8:1];
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@ -30,7 +30,7 @@ module zx_ula(
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output snd_r,
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inout reg ps2_clk,
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inout reg ps2_data,
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inout reg ps2_dat,
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input sd_cd,
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input sd_miso_tape_in,
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@ -51,6 +51,7 @@ pll pll0(.inclk0(clk_in), .c0(clk40), .c1(clk20), .locked(rst_n));
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timings_t timings;
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turbo_t turbo;
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wire clkwait;
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wire screen_read;
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reg n_iorq_delayed, a_valid;
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always @(posedge clk28) begin
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@ -58,18 +59,16 @@ always @(posedge clk28) begin
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a_valid <= screen_read == 0;
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end
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cpu_bus bus();
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always @* begin
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bus.a = {a[15:13], va[12:0]};
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bus.d = vd;
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bus.iorq = ~n_iorq;
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bus.mreq = ~n_mreq;
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bus.m1 = ~n_m1;
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bus.rfsh = ~n_rfsh;
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bus.rd = ~n_rd;
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bus.wr = ~n_wr;
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bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0 && a_valid;
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bus.a_valid = a_valid;
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end
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assign bus.a = {a[15:13], va[12:0]};
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assign bus.d = vd;
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assign bus.iorq = ~n_iorq;
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assign bus.mreq = ~n_mreq;
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assign bus.m1 = ~n_m1;
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assign bus.rfsh = ~n_rfsh;
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assign bus.rd = ~n_rd;
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assign bus.wr = ~n_wr;
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assign bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0 && a_valid;
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assign bus.a_valid = a_valid;
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|
||||
|
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/* KEYBOARD */
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@ -82,7 +81,7 @@ ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
|
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.rst_n(rst_n),
|
||||
.clk(clk28),
|
||||
.ps2_clk_in(ps2_clk),
|
||||
.ps2_dat_in(ps2_data),
|
||||
.ps2_dat_in(ps2_dat),
|
||||
.ps2_clk_out(ps2_clk_out),
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.ps2_dat_out(ps2_dat_out),
|
||||
.zxkb_addr(bus.a[15:8]),
|
||||
@ -97,7 +96,7 @@ ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
|
||||
.joy_fire(joy_fire)
|
||||
);
|
||||
assign ps2_clk = (ps2_clk_out == 0)? 1'b0 : 1'bz;
|
||||
assign ps2_data = (ps2_dat_out == 0)? 1'b0 : 1'bz;
|
||||
assign ps2_dat = (ps2_dat_out == 0)? 1'b0 : 1'bz;
|
||||
|
||||
|
||||
/* SCREEN CONTROLLER */
|
||||
@ -110,7 +109,7 @@ reg hsync;
|
||||
reg up_en;
|
||||
wire [5:0] up_ink_addr, up_paper_addr;
|
||||
wire [7:0] up_ink, up_paper;
|
||||
wire screen_read, screen_load, screen_read_up;
|
||||
wire screen_load, screen_read_up;
|
||||
wire [14:0] screen_addr;
|
||||
wire [7:0] attr_next;
|
||||
wire [8:0] vc, hc;
|
||||
@ -130,6 +129,7 @@ screen screen0(
|
||||
.g(g),
|
||||
.b(b),
|
||||
.csync(csync),
|
||||
.vsync(),
|
||||
.hsync(hsync),
|
||||
|
||||
.blink(blink),
|
||||
@ -173,6 +173,7 @@ assign chroma[2] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
|
||||
|
||||
|
||||
/* CPU CONTROLLER */
|
||||
reg [2:0] rampage128;
|
||||
wire div_wait;
|
||||
wire [7:0] cpucontrol_dout;
|
||||
wire cpucontrol_dout_active;
|
||||
@ -249,8 +250,7 @@ wire ports_dout_active;
|
||||
reg beeper, tape_out;
|
||||
reg screenpage;
|
||||
reg rompage128;
|
||||
reg [2:0] rampage128;
|
||||
reg [2:0] rampage_ext;
|
||||
reg [3:0] rampage_ext;
|
||||
reg [2:0] port_1ffd;
|
||||
reg port_dffd_d3;
|
||||
reg port_dffd_d4;
|
||||
@ -351,6 +351,9 @@ mixer mixer0(
|
||||
.sd_r0(soundrive_r0),
|
||||
.sd_r1(soundrive_r1),
|
||||
|
||||
.ay_abc(ay_abc),
|
||||
.ay_mono(ay_mono),
|
||||
|
||||
.dac_l(snd_l),
|
||||
.dac_r(snd_r)
|
||||
);
|
||||
@ -443,7 +446,7 @@ rom2ram rom2ram0(
|
||||
.dataout(rom2ram_dataout)
|
||||
);
|
||||
|
||||
localparam ROM_OFFSET = 24'h00013256;
|
||||
localparam ROM_OFFSET = 24'h13256;
|
||||
wire [23:0] asmi_addr = ROM_OFFSET + rom2ram_rom_address;
|
||||
asmi asmi0(
|
||||
.clkin(rom2ram_clk),
|
||||
|
||||
@ -66,6 +66,8 @@ YM2149 ym2149_0(
|
||||
.ctrl_aymode(1'b1),
|
||||
.port_a_i(8'hff),
|
||||
.port_b_i(8'hff),
|
||||
.port_a_o(),
|
||||
.port_b_o(),
|
||||
.O_AUDIO_A(ay_a0),
|
||||
.O_AUDIO_B(ay_b0),
|
||||
.O_AUDIO_C(ay_c0)
|
||||
@ -83,6 +85,8 @@ YM2149 ym2149_1(
|
||||
.ctrl_aymode(1'b1),
|
||||
.port_a_i(8'hff),
|
||||
.port_b_i(8'hff),
|
||||
.port_a_o(),
|
||||
.port_b_o(),
|
||||
.O_AUDIO_A(ay_a1),
|
||||
.O_AUDIO_B(ay_b1),
|
||||
.O_AUDIO_C(ay_c1)
|
||||
|
||||
@ -70,7 +70,7 @@ endmodule
|
||||
|
||||
|
||||
module ram(q, a, d, we, clk);
|
||||
output[7:0] q;
|
||||
output reg [7:0] q;
|
||||
input [7:0] d;
|
||||
input [5:0] a;
|
||||
input we, clk;
|
||||
|
||||
@ -94,7 +94,7 @@ set_location_assignment PIN_2 -to va[5]
|
||||
set_location_assignment PIN_3 -to vd[4]
|
||||
set_location_assignment PIN_4 -to va[12]
|
||||
set_location_assignment PIN_5 -to va[11]
|
||||
set_location_assignment PIN_20 -to ps2_data
|
||||
set_location_assignment PIN_20 -to ps2_dat
|
||||
set_location_assignment PIN_21 -to ps2_clk
|
||||
set_location_assignment PIN_22 -to chroma[0]
|
||||
set_location_assignment PIN_23 -to chroma[1]
|
||||
|
||||
32
fpga/tb/Makefile
Normal file
32
fpga/tb/Makefile
Normal file
@ -0,0 +1,32 @@
|
||||
export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH}
|
||||
V_AZ80=$(wildcard ./az80/*.v)
|
||||
V_T80=./t80/t80n_pack.vhd ./t80/t80n.vhd ./t80/t80n_alu.vhd ./t80/t80n_mcode.vhd ./t80/t80na.vhd
|
||||
|
||||
all: testbench_zx_ula
|
||||
|
||||
testbench_zx_ula: IVFLAGS+=-I./az80/ -I./t80/ -I../rtl/
|
||||
testbench_zx_ula: V=$@.v ${V_T80} $(wildcard stubs/*.v) $(wildcard ../rtl/*.vhd) $(wildcard ../rtl/*.v) ../rtl/common.sv $(wildcard ../rtl/*.sv)
|
||||
testbench_zx_ula: rom.mem
|
||||
|
||||
xtestbench_%:
|
||||
iverilog -g2005-sv ${IVFLAGS} -o $@.vvp ${V}
|
||||
vvp $@.vvp
|
||||
@rm $@.vvp
|
||||
|
||||
testbench_%:
|
||||
test ! -d work || rm -rf work
|
||||
vlib work
|
||||
test ! -n "$(filter %.v %.sv,${V})" || vlog -quiet -sv $(filter %.v %sv,${V})
|
||||
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
|
||||
vsim ${VSIMFLAGS} -batch -quiet -do 'run -all' $@
|
||||
test ! -r transcript || rm transcript
|
||||
|
||||
%.bin: %.asm
|
||||
sjasmplus $<
|
||||
%.mem: %.bin
|
||||
srec_cat $< -binary -o $@ -vmem 8
|
||||
|
||||
clean:
|
||||
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
|
||||
|
||||
-include Makefile.local
|
||||
141
fpga/tb/az80/address_latch.v
Normal file
141
fpga/tb/az80/address_latch.v
Normal file
@ -0,0 +1,141 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Feb 27 08:13:14 2016"
|
||||
|
||||
module address_latch(
|
||||
ctl_inc_cy,
|
||||
ctl_inc_dec,
|
||||
ctl_al_we,
|
||||
ctl_inc_limit6,
|
||||
ctl_bus_inc_oe,
|
||||
clk,
|
||||
ctl_apin_mux,
|
||||
ctl_apin_mux2,
|
||||
clrpc,
|
||||
nreset,
|
||||
address_is_1,
|
||||
abus,
|
||||
address
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_inc_cy;
|
||||
input wire ctl_inc_dec;
|
||||
input wire ctl_al_we;
|
||||
input wire ctl_inc_limit6;
|
||||
input wire ctl_bus_inc_oe;
|
||||
input wire clk;
|
||||
input wire ctl_apin_mux;
|
||||
input wire ctl_apin_mux2;
|
||||
input wire clrpc;
|
||||
input wire nreset;
|
||||
output wire address_is_1;
|
||||
inout wire [15:0] abus;
|
||||
output wire [15:0] address;
|
||||
|
||||
wire [15:0] abusz;
|
||||
reg [15:0] Q;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire [15:0] SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire [15:0] SYNTHESIZED_WIRE_5;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
Q[15:0] <= 16'b0000000000000000;
|
||||
end
|
||||
else
|
||||
if (ctl_al_we)
|
||||
begin
|
||||
Q[15:0] <= abusz[15:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign address_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1);
|
||||
|
||||
assign abusz = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & abus;
|
||||
|
||||
assign abus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[15] : 1'bz;
|
||||
assign abus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[14] : 1'bz;
|
||||
assign abus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[13] : 1'bz;
|
||||
assign abus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[12] : 1'bz;
|
||||
assign abus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[11] : 1'bz;
|
||||
assign abus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[10] : 1'bz;
|
||||
assign abus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[9] : 1'bz;
|
||||
assign abus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[8] : 1'bz;
|
||||
assign abus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[7] : 1'bz;
|
||||
assign abus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[6] : 1'bz;
|
||||
assign abus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[5] : 1'bz;
|
||||
assign abus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[4] : 1'bz;
|
||||
assign abus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[3] : 1'bz;
|
||||
assign abus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[2] : 1'bz;
|
||||
assign abus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[1] : 1'bz;
|
||||
assign abus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8];
|
||||
|
||||
|
||||
address_mux b2v_inst7(
|
||||
.select(ctl_apin_mux2),
|
||||
.in0(SYNTHESIZED_WIRE_5),
|
||||
.in1(Q),
|
||||
.out(address));
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ~clrpc;
|
||||
|
||||
|
||||
inc_dec b2v_inst_inc_dec(
|
||||
.limit6(ctl_inc_limit6),
|
||||
.decrement(ctl_inc_dec),
|
||||
.carry_in(ctl_inc_cy),
|
||||
.d(Q),
|
||||
.address(SYNTHESIZED_WIRE_7));
|
||||
|
||||
|
||||
address_mux b2v_mux(
|
||||
.select(ctl_apin_mux),
|
||||
.in0(abusz),
|
||||
.in1(SYNTHESIZED_WIRE_7),
|
||||
.out(SYNTHESIZED_WIRE_5));
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ~Q[0];
|
||||
|
||||
|
||||
endmodule
|
||||
61
fpga/tb/az80/address_mux.v
Normal file
61
fpga/tb/az80/address_mux.v
Normal file
@ -0,0 +1,61 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Nov 08 09:37:58 2014"
|
||||
|
||||
module address_mux(
|
||||
select,
|
||||
in0,
|
||||
in1,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire select;
|
||||
input wire [15:0] in0;
|
||||
input wire [15:0] in1;
|
||||
output wire [15:0] out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire [15:0] SYNTHESIZED_WIRE_1;
|
||||
wire [15:0] SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = in0 & {SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0};
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = in1 & {select,select,select,select,select,select,select,select,select,select,select,select,select,select,select,select};
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~select;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
endmodule
|
||||
82
fpga/tb/az80/address_pins.v
Normal file
82
fpga/tb/az80/address_pins.v
Normal file
@ -0,0 +1,82 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sun Nov 16 16:56:05 2014"
|
||||
|
||||
module address_pins(
|
||||
clk,
|
||||
bus_ab_pin_we,
|
||||
pin_control_oe,
|
||||
address,
|
||||
abus
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire bus_ab_pin_we;
|
||||
input wire pin_control_oe;
|
||||
input wire [15:0] address;
|
||||
output wire [15:0] abus;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
reg [15:0] DFFE_apin_latch;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_0)
|
||||
begin
|
||||
if (bus_ab_pin_we)
|
||||
begin
|
||||
DFFE_apin_latch[15:0] <= address[15:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign abus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz;
|
||||
assign abus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz;
|
||||
assign abus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz;
|
||||
assign abus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz;
|
||||
assign abus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz;
|
||||
assign abus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz;
|
||||
assign abus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz;
|
||||
assign abus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz;
|
||||
assign abus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz;
|
||||
assign abus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz;
|
||||
assign abus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz;
|
||||
assign abus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz;
|
||||
assign abus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz;
|
||||
assign abus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz;
|
||||
assign abus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz;
|
||||
assign abus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~clk;
|
||||
|
||||
|
||||
endmodule
|
||||
397
fpga/tb/az80/alu.v
Normal file
397
fpga/tb/az80/alu.v
Normal file
@ -0,0 +1,397 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Nov 07 19:44:45 2014"
|
||||
|
||||
module alu(
|
||||
alu_core_R,
|
||||
alu_core_V,
|
||||
alu_core_S,
|
||||
alu_bs_oe,
|
||||
alu_parity_in,
|
||||
alu_oe,
|
||||
alu_shift_oe,
|
||||
alu_core_cf_in,
|
||||
alu_op2_oe,
|
||||
alu_op1_oe,
|
||||
alu_res_oe,
|
||||
alu_op1_sel_low,
|
||||
alu_op1_sel_zero,
|
||||
alu_op1_sel_bus,
|
||||
alu_op2_sel_zero,
|
||||
alu_op2_sel_bus,
|
||||
alu_op2_sel_lq,
|
||||
alu_op_low,
|
||||
alu_shift_in,
|
||||
alu_sel_op2_neg,
|
||||
alu_sel_op2_high,
|
||||
alu_shift_left,
|
||||
alu_shift_right,
|
||||
clk,
|
||||
bsel,
|
||||
alu_zero,
|
||||
alu_parity_out,
|
||||
alu_high_eq_9,
|
||||
alu_high_gt_9,
|
||||
alu_low_gt_9,
|
||||
alu_shift_db0,
|
||||
alu_shift_db7,
|
||||
alu_core_cf_out,
|
||||
alu_sf_out,
|
||||
alu_yf_out,
|
||||
alu_xf_out,
|
||||
alu_vf_out,
|
||||
db,
|
||||
test_db_high,
|
||||
test_db_low
|
||||
);
|
||||
|
||||
|
||||
input wire alu_core_R;
|
||||
input wire alu_core_V;
|
||||
input wire alu_core_S;
|
||||
input wire alu_bs_oe;
|
||||
input wire alu_parity_in;
|
||||
input wire alu_oe;
|
||||
input wire alu_shift_oe;
|
||||
input wire alu_core_cf_in;
|
||||
input wire alu_op2_oe;
|
||||
input wire alu_op1_oe;
|
||||
input wire alu_res_oe;
|
||||
input wire alu_op1_sel_low;
|
||||
input wire alu_op1_sel_zero;
|
||||
input wire alu_op1_sel_bus;
|
||||
input wire alu_op2_sel_zero;
|
||||
input wire alu_op2_sel_bus;
|
||||
input wire alu_op2_sel_lq;
|
||||
input wire alu_op_low;
|
||||
input wire alu_shift_in;
|
||||
input wire alu_sel_op2_neg;
|
||||
input wire alu_sel_op2_high;
|
||||
input wire alu_shift_left;
|
||||
input wire alu_shift_right;
|
||||
input wire clk;
|
||||
input wire [2:0] bsel;
|
||||
output wire alu_zero;
|
||||
output wire alu_parity_out;
|
||||
output wire alu_high_eq_9;
|
||||
output wire alu_high_gt_9;
|
||||
output wire alu_low_gt_9;
|
||||
output wire alu_shift_db0;
|
||||
output wire alu_shift_db7;
|
||||
output wire alu_core_cf_out;
|
||||
output wire alu_sf_out;
|
||||
output wire alu_yf_out;
|
||||
output wire alu_xf_out;
|
||||
output wire alu_vf_out;
|
||||
inout wire [7:0] db;
|
||||
output wire [3:0] test_db_high;
|
||||
output wire [3:0] test_db_low;
|
||||
|
||||
wire [3:0] alu_op1;
|
||||
wire [3:0] alu_op2;
|
||||
wire [3:0] db_high;
|
||||
wire [3:0] db_low;
|
||||
reg [3:0] op1_high;
|
||||
reg [3:0] op1_low;
|
||||
reg [3:0] op2_high;
|
||||
reg [3:0] op2_low;
|
||||
wire [3:0] result_hi;
|
||||
reg [3:0] result_lo;
|
||||
wire [3:0] SYNTHESIZED_WIRE_0;
|
||||
wire [3:0] SYNTHESIZED_WIRE_1;
|
||||
wire [3:0] SYNTHESIZED_WIRE_2;
|
||||
wire [3:0] SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire [3:0] SYNTHESIZED_WIRE_5;
|
||||
wire [3:0] SYNTHESIZED_WIRE_7;
|
||||
wire [3:0] SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire [3:0] SYNTHESIZED_WIRE_10;
|
||||
wire [3:0] SYNTHESIZED_WIRE_11;
|
||||
wire [3:0] SYNTHESIZED_WIRE_12;
|
||||
wire [3:0] SYNTHESIZED_WIRE_13;
|
||||
wire [3:0] SYNTHESIZED_WIRE_14;
|
||||
wire [3:0] SYNTHESIZED_WIRE_15;
|
||||
wire [3:0] SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire [3:0] SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire [3:0] SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
wire [3:0] SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_26;
|
||||
wire [3:0] SYNTHESIZED_WIRE_27;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire [3:0] SYNTHESIZED_WIRE_33;
|
||||
wire [3:0] SYNTHESIZED_WIRE_34;
|
||||
|
||||
|
||||
|
||||
|
||||
assign db_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz;
|
||||
assign db_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz;
|
||||
assign db_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz;
|
||||
assign db_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz;
|
||||
assign db_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz;
|
||||
assign db_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz;
|
||||
assign db_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz;
|
||||
|
||||
|
||||
alu_core b2v_core(
|
||||
.cy_in(alu_core_cf_in),
|
||||
.S(alu_core_S),
|
||||
.V(alu_core_V),
|
||||
.R(alu_core_R),
|
||||
.op1(alu_op1),
|
||||
.op2(alu_op2),
|
||||
.cy_out(alu_core_cf_out),
|
||||
.vf_out(alu_vf_out),
|
||||
.result(result_hi));
|
||||
|
||||
assign db[3] = alu_oe ? db_low[3] : 1'bz;
|
||||
assign db[2] = alu_oe ? db_low[2] : 1'bz;
|
||||
assign db[1] = alu_oe ? db_low[1] : 1'bz;
|
||||
assign db[0] = alu_oe ? db_low[0] : 1'bz;
|
||||
|
||||
assign db[7] = alu_oe ? db_high[3] : 1'bz;
|
||||
assign db[6] = alu_oe ? db_high[2] : 1'bz;
|
||||
assign db[5] = alu_oe ? db_high[1] : 1'bz;
|
||||
assign db[4] = alu_oe ? db_high[0] : 1'bz;
|
||||
|
||||
|
||||
alu_bit_select b2v_input_bit_select(
|
||||
.bsel(bsel),
|
||||
.bs_out_high(SYNTHESIZED_WIRE_1),
|
||||
.bs_out_low(SYNTHESIZED_WIRE_0));
|
||||
|
||||
|
||||
alu_shifter_core b2v_input_shift(
|
||||
.shift_in(alu_shift_in),
|
||||
.shift_left(alu_shift_left),
|
||||
.shift_right(alu_shift_right),
|
||||
.db(db),
|
||||
.shift_db0(alu_shift_db0),
|
||||
.shift_db7(alu_shift_db7),
|
||||
.out_high(SYNTHESIZED_WIRE_34),
|
||||
.out_low(SYNTHESIZED_WIRE_33));
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (alu_op_low)
|
||||
begin
|
||||
result_lo[3:0] <= result_hi[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign alu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = ~alu_op_low;
|
||||
|
||||
assign db_low[3] = alu_op2_oe ? op2_low[3] : 1'bz;
|
||||
assign db_low[2] = alu_op2_oe ? op2_low[2] : 1'bz;
|
||||
assign db_low[1] = alu_op2_oe ? op2_low[1] : 1'bz;
|
||||
assign db_low[0] = alu_op2_oe ? op2_low[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_op2_oe ? op2_high[3] : 1'bz;
|
||||
assign db_high[2] = alu_op2_oe ? op2_high[2] : 1'bz;
|
||||
assign db_high[1] = alu_op2_oe ? op2_high[1] : 1'bz;
|
||||
assign db_high[0] = alu_op2_oe ? op2_high[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ~op2_low;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~op2_high;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9};
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign alu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = ~alu_sel_op2_neg;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = ~alu_sel_op2_high;
|
||||
|
||||
assign db_low[3] = alu_res_oe ? result_lo[3] : 1'bz;
|
||||
assign db_low[2] = alu_res_oe ? result_lo[2] : 1'bz;
|
||||
assign db_low[1] = alu_res_oe ? result_lo[1] : 1'bz;
|
||||
assign db_low[0] = alu_res_oe ? result_lo[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_res_oe ? result_hi[3] : 1'bz;
|
||||
assign db_high[2] = alu_res_oe ? result_hi[2] : 1'bz;
|
||||
assign db_high[1] = alu_res_oe ? result_hi[1] : 1'bz;
|
||||
assign db_high[0] = alu_res_oe ? result_hi[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low};
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high;
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_20)
|
||||
begin
|
||||
op1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_23)
|
||||
begin
|
||||
op1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_37)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_26)
|
||||
begin
|
||||
op2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_37)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
op2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign db_low[3] = alu_op1_oe ? op1_low[3] : 1'bz;
|
||||
assign db_low[2] = alu_op1_oe ? op1_low[2] : 1'bz;
|
||||
assign db_low[1] = alu_op1_oe ? op1_low[1] : 1'bz;
|
||||
assign db_low[0] = alu_op1_oe ? op1_low[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_op1_oe ? op1_high[3] : 1'bz;
|
||||
assign db_high[2] = alu_op1_oe ? op1_high[2] : 1'bz;
|
||||
assign db_high[1] = alu_op1_oe ? op1_high[1] : 1'bz;
|
||||
assign db_high[0] = alu_op1_oe ? op1_high[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = ~clk;
|
||||
|
||||
assign SYNTHESIZED_WIRE_37 = ~clk;
|
||||
|
||||
|
||||
alu_mux_2z b2v_op1_latch_mux_high(
|
||||
.sel_a(alu_op1_sel_bus),
|
||||
.sel_zero(alu_op1_sel_zero),
|
||||
.a(db_high),
|
||||
.ena(SYNTHESIZED_WIRE_20),
|
||||
.Q(SYNTHESIZED_WIRE_18));
|
||||
|
||||
|
||||
alu_mux_3z b2v_op1_latch_mux_low(
|
||||
.sel_a(alu_op1_sel_bus),
|
||||
.sel_b(alu_op1_sel_low),
|
||||
.sel_zero(alu_op1_sel_zero),
|
||||
.a(db_low),
|
||||
.b(db_high),
|
||||
.ena(SYNTHESIZED_WIRE_23),
|
||||
.Q(SYNTHESIZED_WIRE_21));
|
||||
|
||||
|
||||
alu_mux_3z b2v_op2_latch_mux_high(
|
||||
.sel_a(alu_op2_sel_bus),
|
||||
.sel_b(alu_op2_sel_lq),
|
||||
.sel_zero(alu_op2_sel_zero),
|
||||
.a(db_high),
|
||||
.b(db_low),
|
||||
.ena(SYNTHESIZED_WIRE_26),
|
||||
.Q(SYNTHESIZED_WIRE_24));
|
||||
|
||||
|
||||
alu_mux_3z b2v_op2_latch_mux_low(
|
||||
.sel_a(alu_op2_sel_bus),
|
||||
.sel_b(alu_op2_sel_lq),
|
||||
.sel_zero(alu_op2_sel_zero),
|
||||
.a(db_low),
|
||||
.b(alu_op1),
|
||||
.ena(SYNTHESIZED_WIRE_29),
|
||||
.Q(SYNTHESIZED_WIRE_27));
|
||||
|
||||
assign alu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3];
|
||||
|
||||
|
||||
alu_prep_daa b2v_prep_daa(
|
||||
.high(op1_high),
|
||||
.low(op1_low),
|
||||
.low_gt_9(alu_low_gt_9),
|
||||
.high_gt_9(alu_high_gt_9),
|
||||
.high_eq_9(alu_high_eq_9));
|
||||
|
||||
assign db_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz;
|
||||
assign db_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz;
|
||||
assign db_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz;
|
||||
assign db_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz;
|
||||
|
||||
assign db_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz;
|
||||
assign db_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz;
|
||||
assign db_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz;
|
||||
assign db_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz;
|
||||
|
||||
assign alu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]);
|
||||
|
||||
assign alu_sf_out = db_high[3];
|
||||
assign alu_yf_out = db_high[1];
|
||||
assign alu_xf_out = db_low[3];
|
||||
assign test_db_high = db_high;
|
||||
assign test_db_low = db_low;
|
||||
|
||||
endmodule
|
||||
77
fpga/tb/az80/alu_bit_select.v
Normal file
77
fpga/tb/az80/alu_bit_select.v
Normal file
@ -0,0 +1,77 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:21:31 2014"
|
||||
|
||||
module alu_bit_select(
|
||||
bsel,
|
||||
bs_out_high,
|
||||
bs_out_low
|
||||
);
|
||||
|
||||
|
||||
input wire [2:0] bsel;
|
||||
output wire [3:0] bs_out_high;
|
||||
output wire [3:0] bs_out_low;
|
||||
|
||||
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
|
||||
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
|
||||
|
||||
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];
|
||||
|
||||
assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = ~bsel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = ~bsel[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = ~bsel[2];
|
||||
|
||||
assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED;
|
||||
assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
263
fpga/tb/az80/alu_control.v
Normal file
263
fpga/tb/az80/alu_control.v
Normal file
@ -0,0 +1,263 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Tue Oct 21 20:41:52 2014"
|
||||
|
||||
module alu_control(
|
||||
alu_shift_db0,
|
||||
alu_shift_db7,
|
||||
ctl_shift_en,
|
||||
alu_low_gt_9,
|
||||
alu_high_gt_9,
|
||||
alu_high_eq_9,
|
||||
ctl_daa_oe,
|
||||
ctl_alu_op_low,
|
||||
alu_parity_out,
|
||||
flags_cf,
|
||||
flags_zf,
|
||||
flags_pf,
|
||||
flags_sf,
|
||||
ctl_cond_short,
|
||||
alu_vf_out,
|
||||
iff2,
|
||||
ctl_alu_core_hf,
|
||||
ctl_eval_cond,
|
||||
repeat_en,
|
||||
flags_cf_latch,
|
||||
flags_hf2,
|
||||
flags_hf,
|
||||
ctl_66_oe,
|
||||
clk,
|
||||
ctl_pf_sel,
|
||||
op543,
|
||||
alu_shift_in,
|
||||
alu_shift_right,
|
||||
alu_shift_left,
|
||||
shift_cf_out,
|
||||
alu_parity_in,
|
||||
flags_cond_true,
|
||||
daa_cf_out,
|
||||
pf_sel,
|
||||
alu_op_low,
|
||||
alu_core_cf_in,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire alu_shift_db0;
|
||||
input wire alu_shift_db7;
|
||||
input wire ctl_shift_en;
|
||||
input wire alu_low_gt_9;
|
||||
input wire alu_high_gt_9;
|
||||
input wire alu_high_eq_9;
|
||||
input wire ctl_daa_oe;
|
||||
input wire ctl_alu_op_low;
|
||||
input wire alu_parity_out;
|
||||
input wire flags_cf;
|
||||
input wire flags_zf;
|
||||
input wire flags_pf;
|
||||
input wire flags_sf;
|
||||
input wire ctl_cond_short;
|
||||
input wire alu_vf_out;
|
||||
input wire iff2;
|
||||
input wire ctl_alu_core_hf;
|
||||
input wire ctl_eval_cond;
|
||||
input wire repeat_en;
|
||||
input wire flags_cf_latch;
|
||||
input wire flags_hf2;
|
||||
input wire flags_hf;
|
||||
input wire ctl_66_oe;
|
||||
input wire clk;
|
||||
input wire [1:0] ctl_pf_sel;
|
||||
input wire [2:0] op543;
|
||||
output wire alu_shift_in;
|
||||
output wire alu_shift_right;
|
||||
output wire alu_shift_left;
|
||||
output wire shift_cf_out;
|
||||
output wire alu_parity_in;
|
||||
output reg flags_cond_true;
|
||||
output wire daa_cf_out;
|
||||
output wire pf_sel;
|
||||
output wire alu_op_low;
|
||||
output wire alu_core_cf_in;
|
||||
output wire [7:0] db;
|
||||
|
||||
wire condition;
|
||||
wire [7:0] out;
|
||||
wire [1:0] sel;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
reg DFFE_latch_pf_tmp;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign alu_op_low = ctl_alu_op_low;
|
||||
assign daa_cf_out = SYNTHESIZED_WIRE_21;
|
||||
assign SYNTHESIZED_WIRE_22 = 0;
|
||||
assign SYNTHESIZED_WIRE_18 = 1;
|
||||
|
||||
|
||||
|
||||
assign condition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1;
|
||||
|
||||
|
||||
|
||||
assign db[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz;
|
||||
assign db[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz;
|
||||
assign db[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz;
|
||||
assign db[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz;
|
||||
assign db[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz;
|
||||
assign db[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz;
|
||||
assign db[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz;
|
||||
assign db[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz;
|
||||
|
||||
assign alu_shift_right = ctl_shift_en & op543[0];
|
||||
|
||||
assign alu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe;
|
||||
|
||||
assign sel[0] = op543[1];
|
||||
|
||||
|
||||
assign out[1] = SYNTHESIZED_WIRE_20;
|
||||
|
||||
|
||||
assign out[2] = SYNTHESIZED_WIRE_20;
|
||||
|
||||
|
||||
assign out[5] = SYNTHESIZED_WIRE_21;
|
||||
|
||||
|
||||
assign out[6] = SYNTHESIZED_WIRE_21;
|
||||
|
||||
|
||||
assign alu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~op543[0];
|
||||
|
||||
assign sel[1] = op543[2] & SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11;
|
||||
|
||||
assign shift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf;
|
||||
|
||||
assign alu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = ~ctl_alu_core_hf;
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_eval_cond)
|
||||
begin
|
||||
flags_cond_true <= condition;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
alu_mux_4 b2v_inst_cond_mux(
|
||||
.in0(flags_zf),
|
||||
.in1(flags_cf),
|
||||
.in2(flags_pf),
|
||||
.in3(flags_sf),
|
||||
.sel(sel),
|
||||
.out(SYNTHESIZED_WIRE_1));
|
||||
|
||||
|
||||
alu_mux_4 b2v_inst_pf_sel(
|
||||
.in0(alu_parity_out),
|
||||
.in1(alu_vf_out),
|
||||
.in2(iff2),
|
||||
.in3(repeat_en),
|
||||
.sel(ctl_pf_sel),
|
||||
.out(pf_sel));
|
||||
|
||||
|
||||
alu_mux_8 b2v_inst_shift_mux(
|
||||
.in0(alu_shift_db7),
|
||||
.in1(alu_shift_db0),
|
||||
.in2(flags_cf_latch),
|
||||
.in3(flags_cf_latch),
|
||||
.in4(SYNTHESIZED_WIRE_22),
|
||||
.in5(alu_shift_db7),
|
||||
.in6(SYNTHESIZED_WIRE_18),
|
||||
.in7(SYNTHESIZED_WIRE_22),
|
||||
.sel(op543),
|
||||
.out(alu_shift_in));
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_alu_op_low)
|
||||
begin
|
||||
DFFE_latch_pf_tmp <= alu_parity_out;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~op543[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = ~op543[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = ~ctl_cond_short;
|
||||
|
||||
|
||||
assign out[3] = 0;
|
||||
assign out[7] = 0;
|
||||
assign out[0] = 0;
|
||||
assign out[4] = 0;
|
||||
|
||||
endmodule
|
||||
113
fpga/tb/az80/alu_core.v
Normal file
113
fpga/tb/az80/alu_core.v
Normal file
@ -0,0 +1,113 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:17:04 2014"
|
||||
|
||||
module alu_core(
|
||||
cy_in,
|
||||
S,
|
||||
V,
|
||||
R,
|
||||
op1,
|
||||
op2,
|
||||
cy_out,
|
||||
vf_out,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire cy_in;
|
||||
input wire S;
|
||||
input wire V;
|
||||
input wire R;
|
||||
input wire [3:0] op1;
|
||||
input wire [3:0] op2;
|
||||
output wire cy_out;
|
||||
output wire vf_out;
|
||||
output wire [3:0] result;
|
||||
|
||||
wire [3:0] result_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign cy_out = SYNTHESIZED_WIRE_3;
|
||||
|
||||
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_0(
|
||||
.cy_in(cy_in),
|
||||
.op1(op1[0]),
|
||||
.op2(op2[0]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[0]),
|
||||
.cy_out(SYNTHESIZED_WIRE_0));
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_1(
|
||||
.cy_in(SYNTHESIZED_WIRE_0),
|
||||
.op1(op1[1]),
|
||||
.op2(op2[1]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[1]),
|
||||
.cy_out(SYNTHESIZED_WIRE_1));
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_2(
|
||||
.cy_in(SYNTHESIZED_WIRE_1),
|
||||
.op1(op1[2]),
|
||||
.op2(op2[2]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[2]),
|
||||
.cy_out(SYNTHESIZED_WIRE_5));
|
||||
|
||||
|
||||
alu_slice b2v_alu_slice_bit_3(
|
||||
.cy_in(SYNTHESIZED_WIRE_5),
|
||||
.op1(op1[3]),
|
||||
.op2(op2[3]),
|
||||
.S(S),
|
||||
.V(V),
|
||||
.R(R),
|
||||
.result(result_ALTERA_SYNTHESIZED[3]),
|
||||
.cy_out(SYNTHESIZED_WIRE_3));
|
||||
|
||||
assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign result = result_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
371
fpga/tb/az80/alu_flags.v
Normal file
371
fpga/tb/az80/alu_flags.v
Normal file
@ -0,0 +1,371 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 09:01:30 2016"
|
||||
|
||||
module alu_flags(
|
||||
ctl_flags_oe,
|
||||
ctl_flags_bus,
|
||||
ctl_flags_alu,
|
||||
alu_sf_out,
|
||||
alu_yf_out,
|
||||
alu_xf_out,
|
||||
ctl_flags_nf_set,
|
||||
alu_zero,
|
||||
shift_cf_out,
|
||||
alu_core_cf_out,
|
||||
daa_cf_out,
|
||||
ctl_flags_cf_set,
|
||||
ctl_flags_cf_cpl,
|
||||
pf_sel,
|
||||
ctl_flags_cf_we,
|
||||
ctl_flags_sz_we,
|
||||
ctl_flags_xy_we,
|
||||
ctl_flags_hf_we,
|
||||
ctl_flags_pf_we,
|
||||
ctl_flags_nf_we,
|
||||
ctl_flags_cf2_we,
|
||||
ctl_flags_hf_cpl,
|
||||
ctl_flags_use_cf2,
|
||||
ctl_flags_hf2_we,
|
||||
ctl_flags_nf_clr,
|
||||
ctl_alu_zero_16bit,
|
||||
clk,
|
||||
ctl_flags_cf2_sel_shift,
|
||||
ctl_flags_cf2_sel_daa,
|
||||
nhold_clk_wait,
|
||||
flags_sf,
|
||||
flags_zf,
|
||||
flags_hf,
|
||||
flags_pf,
|
||||
flags_cf,
|
||||
flags_nf,
|
||||
flags_cf_latch,
|
||||
flags_hf2,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_flags_oe;
|
||||
input wire ctl_flags_bus;
|
||||
input wire ctl_flags_alu;
|
||||
input wire alu_sf_out;
|
||||
input wire alu_yf_out;
|
||||
input wire alu_xf_out;
|
||||
input wire ctl_flags_nf_set;
|
||||
input wire alu_zero;
|
||||
input wire shift_cf_out;
|
||||
input wire alu_core_cf_out;
|
||||
input wire daa_cf_out;
|
||||
input wire ctl_flags_cf_set;
|
||||
input wire ctl_flags_cf_cpl;
|
||||
input wire pf_sel;
|
||||
input wire ctl_flags_cf_we;
|
||||
input wire ctl_flags_sz_we;
|
||||
input wire ctl_flags_xy_we;
|
||||
input wire ctl_flags_hf_we;
|
||||
input wire ctl_flags_pf_we;
|
||||
input wire ctl_flags_nf_we;
|
||||
input wire ctl_flags_cf2_we;
|
||||
input wire ctl_flags_hf_cpl;
|
||||
input wire ctl_flags_use_cf2;
|
||||
input wire ctl_flags_hf2_we;
|
||||
input wire ctl_flags_nf_clr;
|
||||
input wire ctl_alu_zero_16bit;
|
||||
input wire clk;
|
||||
input wire ctl_flags_cf2_sel_shift;
|
||||
input wire ctl_flags_cf2_sel_daa;
|
||||
input wire nhold_clk_wait;
|
||||
output wire flags_sf;
|
||||
output wire flags_zf;
|
||||
output wire flags_hf;
|
||||
output wire flags_pf;
|
||||
output wire flags_cf;
|
||||
output wire flags_nf;
|
||||
output wire flags_cf_latch;
|
||||
output reg flags_hf2;
|
||||
inout wire [7:0] db;
|
||||
|
||||
reg flags_xf;
|
||||
reg flags_yf;
|
||||
wire [1:0] sel;
|
||||
reg DFFE_inst_latch_hf;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
reg SYNTHESIZED_WIRE_39;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
reg DFFE_inst_latch_sf;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
reg DFFE_inst_latch_pf;
|
||||
reg DFFE_inst_latch_nf;
|
||||
wire SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_26;
|
||||
wire SYNTHESIZED_WIRE_27;
|
||||
wire SYNTHESIZED_WIRE_28;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_40;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire SYNTHESIZED_WIRE_33;
|
||||
wire SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
reg DFFE_inst_latch_cf;
|
||||
reg DFFE_inst_latch_cf2;
|
||||
wire SYNTHESIZED_WIRE_38;
|
||||
|
||||
assign flags_sf = DFFE_inst_latch_sf;
|
||||
assign flags_zf = SYNTHESIZED_WIRE_39;
|
||||
assign flags_hf = SYNTHESIZED_WIRE_23;
|
||||
assign flags_pf = DFFE_inst_latch_pf;
|
||||
assign flags_cf = SYNTHESIZED_WIRE_24;
|
||||
assign flags_nf = DFFE_inst_latch_nf;
|
||||
assign flags_cf_latch = DFFE_inst_latch_cf;
|
||||
assign SYNTHESIZED_WIRE_38 = 0;
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
|
||||
|
||||
assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = ~ctl_flags_cf2_we;
|
||||
|
||||
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;
|
||||
|
||||
assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
|
||||
|
||||
assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
|
||||
|
||||
assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
|
||||
|
||||
assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;
|
||||
|
||||
assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
|
||||
|
||||
assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
|
||||
|
||||
assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
|
||||
|
||||
assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
|
||||
|
||||
assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
|
||||
|
||||
assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_27)
|
||||
begin
|
||||
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_29)
|
||||
begin
|
||||
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_hf_we)
|
||||
begin
|
||||
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_hf2_we)
|
||||
begin
|
||||
flags_hf2 <= SYNTHESIZED_WIRE_40;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_nf_we)
|
||||
begin
|
||||
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_pf_we)
|
||||
begin
|
||||
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_sz_we)
|
||||
begin
|
||||
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_xy_we)
|
||||
begin
|
||||
flags_xf <= SYNTHESIZED_WIRE_35;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_xy_we)
|
||||
begin
|
||||
flags_yf <= SYNTHESIZED_WIRE_36;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (ctl_flags_sz_we)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
alu_mux_2 b2v_inst_mux_cf(
|
||||
.in0(DFFE_inst_latch_cf),
|
||||
.in1(DFFE_inst_latch_cf2),
|
||||
.sel1(ctl_flags_use_cf2),
|
||||
.out(SYNTHESIZED_WIRE_25));
|
||||
|
||||
|
||||
alu_mux_4 b2v_inst_mux_cf2(
|
||||
.in0(alu_core_cf_out),
|
||||
.in1(shift_cf_out),
|
||||
.in2(daa_cf_out),
|
||||
.in3(SYNTHESIZED_WIRE_38),
|
||||
.sel(sel),
|
||||
.out(SYNTHESIZED_WIRE_28));
|
||||
|
||||
assign sel[0] = ctl_flags_cf2_sel_shift;
|
||||
assign sel[1] = ctl_flags_cf2_sel_daa;
|
||||
|
||||
endmodule
|
||||
61
fpga/tb/az80/alu_mux_2.v
Normal file
61
fpga/tb/az80/alu_mux_2.v
Normal file
@ -0,0 +1,61 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:10:35 2014"
|
||||
|
||||
module alu_mux_2(
|
||||
sel1,
|
||||
in1,
|
||||
in0,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire sel1;
|
||||
input wire in1;
|
||||
input wire in0;
|
||||
output wire out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = in0 & SYNTHESIZED_WIRE_0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = in1 & sel1;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~sel1;
|
||||
|
||||
|
||||
endmodule
|
||||
62
fpga/tb/az80/alu_mux_2z.v
Normal file
62
fpga/tb/az80/alu_mux_2z.v
Normal file
@ -0,0 +1,62 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Oct 31 21:18:33 2014"
|
||||
|
||||
module alu_mux_2z(
|
||||
sel_a,
|
||||
sel_zero,
|
||||
a,
|
||||
ena,
|
||||
Q
|
||||
);
|
||||
|
||||
|
||||
input wire sel_a;
|
||||
input wire sel_zero;
|
||||
input wire [3:0] a;
|
||||
output wire ena;
|
||||
output wire [3:0] Q;
|
||||
|
||||
wire [3:0] SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a};
|
||||
|
||||
assign ena = sel_a | sel_zero;
|
||||
|
||||
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
|
||||
|
||||
|
||||
endmodule
|
||||
72
fpga/tb/az80/alu_mux_3z.v
Normal file
72
fpga/tb/az80/alu_mux_3z.v
Normal file
@ -0,0 +1,72 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Oct 31 21:08:42 2014"
|
||||
|
||||
module alu_mux_3z(
|
||||
sel_zero,
|
||||
sel_a,
|
||||
sel_b,
|
||||
a,
|
||||
b,
|
||||
ena,
|
||||
Q
|
||||
);
|
||||
|
||||
|
||||
input wire sel_zero;
|
||||
input wire sel_a;
|
||||
input wire sel_b;
|
||||
input wire [3:0] a;
|
||||
input wire [3:0] b;
|
||||
output wire ena;
|
||||
output wire [3:0] Q;
|
||||
|
||||
wire [3:0] SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire [3:0] SYNTHESIZED_WIRE_2;
|
||||
wire [3:0] SYNTHESIZED_WIRE_3;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a};
|
||||
|
||||
assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~sel_zero;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign ena = sel_a | sel_b | sel_zero;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b};
|
||||
|
||||
|
||||
endmodule
|
||||
74
fpga/tb/az80/alu_mux_4.v
Normal file
74
fpga/tb/az80/alu_mux_4.v
Normal file
@ -0,0 +1,74 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:05:38 2014"
|
||||
|
||||
module alu_mux_4(
|
||||
in0,
|
||||
in1,
|
||||
in2,
|
||||
in3,
|
||||
sel,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire in0;
|
||||
input wire in1;
|
||||
input wire in2;
|
||||
input wire in3;
|
||||
input wire [1:0] sel;
|
||||
output wire out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & in0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = sel[0] & SYNTHESIZED_WIRE_9 & in1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 & sel[1] & in2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = sel[0] & sel[1] & in3;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = ~sel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = ~sel[1];
|
||||
|
||||
|
||||
endmodule
|
||||
97
fpga/tb/az80/alu_mux_8.v
Normal file
97
fpga/tb/az80/alu_mux_8.v
Normal file
@ -0,0 +1,97 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:04:13 2014"
|
||||
|
||||
module alu_mux_8(
|
||||
in0,
|
||||
in1,
|
||||
in2,
|
||||
in3,
|
||||
in4,
|
||||
in5,
|
||||
in6,
|
||||
in7,
|
||||
sel,
|
||||
out
|
||||
);
|
||||
|
||||
|
||||
input wire in0;
|
||||
input wire in1;
|
||||
input wire in2;
|
||||
input wire in3;
|
||||
input wire in4;
|
||||
input wire in5;
|
||||
input wire in6;
|
||||
input wire in7;
|
||||
input wire [2:0] sel;
|
||||
output wire out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7;
|
||||
|
||||
assign out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = ~sel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = ~sel[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_22 = ~sel[2];
|
||||
|
||||
|
||||
endmodule
|
||||
76
fpga/tb/az80/alu_prep_daa.v
Normal file
76
fpga/tb/az80/alu_prep_daa.v
Normal file
@ -0,0 +1,76 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:01:36 2014"
|
||||
|
||||
module alu_prep_daa(
|
||||
high,
|
||||
low,
|
||||
low_gt_9,
|
||||
high_eq_9,
|
||||
high_gt_9
|
||||
);
|
||||
|
||||
|
||||
input wire [3:0] high;
|
||||
input wire [3:0] low;
|
||||
output wire low_gt_9;
|
||||
output wire high_eq_9;
|
||||
output wire high_gt_9;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ~high[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = low[3] & low[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = high[3] & high[2];
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = low[3] & low[1];
|
||||
|
||||
assign low_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = high[3] & high[1];
|
||||
|
||||
assign high_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ~high[1];
|
||||
|
||||
assign high_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;
|
||||
|
||||
|
||||
endmodule
|
||||
127
fpga/tb/az80/alu_select.v
Normal file
127
fpga/tb/az80/alu_select.v
Normal file
@ -0,0 +1,127 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 11:59:39 2014"
|
||||
|
||||
module alu_select(
|
||||
ctl_alu_oe,
|
||||
ctl_alu_shift_oe,
|
||||
ctl_alu_op2_oe,
|
||||
ctl_alu_res_oe,
|
||||
ctl_alu_op1_oe,
|
||||
ctl_alu_bs_oe,
|
||||
ctl_alu_op1_sel_bus,
|
||||
ctl_alu_op1_sel_low,
|
||||
ctl_alu_op1_sel_zero,
|
||||
ctl_alu_op2_sel_zero,
|
||||
ctl_alu_op2_sel_bus,
|
||||
ctl_alu_op2_sel_lq,
|
||||
ctl_alu_sel_op2_neg,
|
||||
ctl_alu_sel_op2_high,
|
||||
ctl_alu_core_R,
|
||||
ctl_alu_core_V,
|
||||
ctl_alu_core_S,
|
||||
alu_oe,
|
||||
alu_shift_oe,
|
||||
alu_op2_oe,
|
||||
alu_res_oe,
|
||||
alu_op1_oe,
|
||||
alu_bs_oe,
|
||||
alu_op1_sel_bus,
|
||||
alu_op1_sel_low,
|
||||
alu_op1_sel_zero,
|
||||
alu_op2_sel_zero,
|
||||
alu_op2_sel_bus,
|
||||
alu_op2_sel_lq,
|
||||
alu_sel_op2_neg,
|
||||
alu_sel_op2_high,
|
||||
alu_core_R,
|
||||
alu_core_V,
|
||||
alu_core_S
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_alu_oe;
|
||||
input wire ctl_alu_shift_oe;
|
||||
input wire ctl_alu_op2_oe;
|
||||
input wire ctl_alu_res_oe;
|
||||
input wire ctl_alu_op1_oe;
|
||||
input wire ctl_alu_bs_oe;
|
||||
input wire ctl_alu_op1_sel_bus;
|
||||
input wire ctl_alu_op1_sel_low;
|
||||
input wire ctl_alu_op1_sel_zero;
|
||||
input wire ctl_alu_op2_sel_zero;
|
||||
input wire ctl_alu_op2_sel_bus;
|
||||
input wire ctl_alu_op2_sel_lq;
|
||||
input wire ctl_alu_sel_op2_neg;
|
||||
input wire ctl_alu_sel_op2_high;
|
||||
input wire ctl_alu_core_R;
|
||||
input wire ctl_alu_core_V;
|
||||
input wire ctl_alu_core_S;
|
||||
output wire alu_oe;
|
||||
output wire alu_shift_oe;
|
||||
output wire alu_op2_oe;
|
||||
output wire alu_res_oe;
|
||||
output wire alu_op1_oe;
|
||||
output wire alu_bs_oe;
|
||||
output wire alu_op1_sel_bus;
|
||||
output wire alu_op1_sel_low;
|
||||
output wire alu_op1_sel_zero;
|
||||
output wire alu_op2_sel_zero;
|
||||
output wire alu_op2_sel_bus;
|
||||
output wire alu_op2_sel_lq;
|
||||
output wire alu_sel_op2_neg;
|
||||
output wire alu_sel_op2_high;
|
||||
output wire alu_core_R;
|
||||
output wire alu_core_V;
|
||||
output wire alu_core_S;
|
||||
|
||||
|
||||
assign alu_oe = ctl_alu_oe;
|
||||
assign alu_shift_oe = ctl_alu_shift_oe;
|
||||
assign alu_op2_oe = ctl_alu_op2_oe;
|
||||
assign alu_res_oe = ctl_alu_res_oe;
|
||||
assign alu_op1_oe = ctl_alu_op1_oe;
|
||||
assign alu_bs_oe = ctl_alu_bs_oe;
|
||||
assign alu_op1_sel_bus = ctl_alu_op1_sel_bus;
|
||||
assign alu_op1_sel_low = ctl_alu_op1_sel_low;
|
||||
assign alu_op1_sel_zero = ctl_alu_op1_sel_zero;
|
||||
assign alu_op2_sel_zero = ctl_alu_op2_sel_zero;
|
||||
assign alu_op2_sel_bus = ctl_alu_op2_sel_bus;
|
||||
assign alu_op2_sel_lq = ctl_alu_op2_sel_lq;
|
||||
assign alu_sel_op2_neg = ctl_alu_sel_op2_neg;
|
||||
assign alu_sel_op2_high = ctl_alu_sel_op2_high;
|
||||
assign alu_core_R = ctl_alu_core_R;
|
||||
assign alu_core_V = ctl_alu_core_V;
|
||||
assign alu_core_S = ctl_alu_core_S;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
155
fpga/tb/az80/alu_shifter_core.v
Normal file
155
fpga/tb/az80/alu_shifter_core.v
Normal file
@ -0,0 +1,155 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 11:55:31 2014"
|
||||
|
||||
module alu_shifter_core(
|
||||
shift_in,
|
||||
shift_right,
|
||||
shift_left,
|
||||
db,
|
||||
shift_db0,
|
||||
shift_db7,
|
||||
out_high,
|
||||
out_low
|
||||
);
|
||||
|
||||
|
||||
input wire shift_in;
|
||||
input wire shift_right;
|
||||
input wire shift_left;
|
||||
input wire [7:0] db;
|
||||
output wire shift_db0;
|
||||
output wire shift_db7;
|
||||
output wire [3:0] out_high;
|
||||
output wire [3:0] out_low;
|
||||
|
||||
wire [3:0] out_high_ALTERA_SYNTHESIZED;
|
||||
wire [3:0] out_low_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
wire SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_26;
|
||||
wire SYNTHESIZED_WIRE_27;
|
||||
wire SYNTHESIZED_WIRE_28;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
|
||||
assign shift_db0 = db[0];
|
||||
assign shift_db7 = db[7];
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = shift_in & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = db[0] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = db[1] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = db[0] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = db[1] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = db[2] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = db[1] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = db[2] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = db[3] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = db[2] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = db[3] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = db[4] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = db[3] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = db[4] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_22 = db[5] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_24 = db[4] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_23 = db[5] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_25 = db[6] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_27 = db[5] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_26 = db[6] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_28 = db[7] & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = db[6] & shift_left;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = db[7] & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_31 = shift_in & shift_right;
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = ~(shift_right | shift_left);
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign out_low_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_20 | SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24 | SYNTHESIZED_WIRE_25;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_26 | SYNTHESIZED_WIRE_27 | SYNTHESIZED_WIRE_28;
|
||||
|
||||
assign out_high_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_29 | SYNTHESIZED_WIRE_30 | SYNTHESIZED_WIRE_31;
|
||||
|
||||
assign out_high = out_high_ALTERA_SYNTHESIZED;
|
||||
assign out_low = out_low_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
89
fpga/tb/az80/alu_slice.v
Normal file
89
fpga/tb/az80/alu_slice.v
Normal file
@ -0,0 +1,89 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 11:51:12 2014"
|
||||
|
||||
module alu_slice(
|
||||
op2,
|
||||
op1,
|
||||
cy_in,
|
||||
R,
|
||||
S,
|
||||
V,
|
||||
cy_out,
|
||||
result
|
||||
);
|
||||
|
||||
|
||||
input wire op2;
|
||||
input wire op1;
|
||||
input wire cy_in;
|
||||
input wire R;
|
||||
input wire S;
|
||||
input wire V;
|
||||
output wire cy_out;
|
||||
output wire result;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = op2 | cy_in | op1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = cy_in & op2 & op1;
|
||||
|
||||
assign result = ~SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4);
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = op2 | op1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = cy_in & SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = op1 & op2;
|
||||
|
||||
assign cy_out = ~(R | SYNTHESIZED_WIRE_10);
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = ~(SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | S);
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = V | SYNTHESIZED_WIRE_10;
|
||||
|
||||
|
||||
endmodule
|
||||
66
fpga/tb/az80/bus_control.v
Normal file
66
fpga/tb/az80/bus_control.v
Normal file
@ -0,0 +1,66 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Feb 26 22:25:37 2016"
|
||||
|
||||
module bus_control(
|
||||
ctl_bus_ff_oe,
|
||||
ctl_bus_zero_oe,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_bus_ff_oe;
|
||||
input wire ctl_bus_zero_oe;
|
||||
inout wire [7:0] db;
|
||||
|
||||
wire [7:0] bus;
|
||||
wire [7:0] vcc;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
|
||||
|
||||
|
||||
|
||||
assign db[7] = SYNTHESIZED_WIRE_0 ? bus[7] : 1'bz;
|
||||
assign db[6] = SYNTHESIZED_WIRE_0 ? bus[6] : 1'bz;
|
||||
assign db[5] = SYNTHESIZED_WIRE_0 ? bus[5] : 1'bz;
|
||||
assign db[4] = SYNTHESIZED_WIRE_0 ? bus[4] : 1'bz;
|
||||
assign db[3] = SYNTHESIZED_WIRE_0 ? bus[3] : 1'bz;
|
||||
assign db[2] = SYNTHESIZED_WIRE_0 ? bus[2] : 1'bz;
|
||||
assign db[1] = SYNTHESIZED_WIRE_0 ? bus[1] : 1'bz;
|
||||
assign db[0] = SYNTHESIZED_WIRE_0 ? bus[0] : 1'bz;
|
||||
|
||||
|
||||
assign bus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ctl_bus_ff_oe | ctl_bus_zero_oe;
|
||||
|
||||
assign vcc = 8'b11111111;
|
||||
|
||||
endmodule
|
||||
54
fpga/tb/az80/bus_switch.v
Normal file
54
fpga/tb/az80/bus_switch.v
Normal file
@ -0,0 +1,54 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
//============================================================================
|
||||
// Bus switch in bus A-Z80 CPU
|
||||
//
|
||||
// Copyright 2014, 2016 Goran Devic
|
||||
//
|
||||
// This module provides control data bus switch signals. The sole purpose of
|
||||
// having these wires defined in this module is to get all control signals
|
||||
// (which are processed by genglobals.py) to appear in the list of global
|
||||
// control signals ("globals.vh") for consistency.
|
||||
//============================================================================
|
||||
|
||||
module bus_switch
|
||||
(
|
||||
input wire ctl_sw_1u, // Control input for the SW1 upstream
|
||||
input wire ctl_sw_1d, // Control input for the SW1 downstream
|
||||
|
||||
input wire ctl_sw_2u, // Control input for the SW2 upstream
|
||||
input wire ctl_sw_2d, // Control input for the SW2 downstream
|
||||
|
||||
input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
|
||||
output wire bus_sw_1u, // SW1 upstream
|
||||
output wire bus_sw_1d, // SW1 downstream
|
||||
|
||||
output wire bus_sw_2u, // SW2 upstream
|
||||
output wire bus_sw_2d, // SW2 downstream
|
||||
|
||||
output wire bus_sw_mask543_en // Affects SW1 downstream
|
||||
);
|
||||
|
||||
assign bus_sw_1u = ctl_sw_1u;
|
||||
assign bus_sw_1d = ctl_sw_1d;
|
||||
|
||||
assign bus_sw_2u = ctl_sw_2u;
|
||||
assign bus_sw_2d = ctl_sw_2d;
|
||||
|
||||
assign bus_sw_mask543_en = ctl_sw_mask543_en;
|
||||
|
||||
endmodule
|
||||
172
fpga/tb/az80/clk_delay.v
Normal file
172
fpga/tb/az80/clk_delay.v
Normal file
@ -0,0 +1,172 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 08:59:31 2016"
|
||||
|
||||
module clk_delay(
|
||||
clk,
|
||||
in_intr,
|
||||
nreset,
|
||||
T1,
|
||||
latch_wait,
|
||||
mwait,
|
||||
M1,
|
||||
busrq,
|
||||
setM1,
|
||||
hold_clk_iorq,
|
||||
hold_clk_wait,
|
||||
iorq_Tw,
|
||||
busack,
|
||||
pin_control_oe,
|
||||
hold_clk_busrq,
|
||||
nhold_clk_wait
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire in_intr;
|
||||
input wire nreset;
|
||||
input wire T1;
|
||||
input wire latch_wait;
|
||||
input wire mwait;
|
||||
input wire M1;
|
||||
input wire busrq;
|
||||
input wire setM1;
|
||||
output wire hold_clk_iorq;
|
||||
output wire hold_clk_wait;
|
||||
output wire iorq_Tw;
|
||||
output wire busack;
|
||||
output wire pin_control_oe;
|
||||
output wire hold_clk_busrq;
|
||||
output wire nhold_clk_wait;
|
||||
|
||||
reg hold_clk_busrq_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
reg DFF_inst5;
|
||||
reg SYNTHESIZED_WIRE_7;
|
||||
reg SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
reg SYNTHESIZED_WIRE_9;
|
||||
|
||||
assign hold_clk_wait = SYNTHESIZED_WIRE_9;
|
||||
assign iorq_Tw = DFF_inst5;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_9 <= 0;
|
||||
end
|
||||
else
|
||||
if (SYNTHESIZED_WIRE_1)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_9 <= mwait;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_8 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_8 <= busrq;
|
||||
end
|
||||
end
|
||||
|
||||
assign hold_clk_iorq = DFF_inst5 | SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign busack = SYNTHESIZED_WIRE_8 & hold_clk_busrq_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign pin_control_oe = SYNTHESIZED_WIRE_3 & nreset;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = hold_clk_busrq_ALTERA_SYNTHESIZED | setM1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = ~hold_clk_busrq_ALTERA_SYNTHESIZED;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_7 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_4;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
hold_clk_busrq_ALTERA_SYNTHESIZED <= 0;
|
||||
end
|
||||
else
|
||||
if (SYNTHESIZED_WIRE_5)
|
||||
begin
|
||||
hold_clk_busrq_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_8;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFF_inst5 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_inst5 <= SYNTHESIZED_WIRE_7;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = in_intr & M1 & T1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = latch_wait | SYNTHESIZED_WIRE_9;
|
||||
|
||||
assign nhold_clk_wait = ~SYNTHESIZED_WIRE_9;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = ~clk;
|
||||
|
||||
assign hold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
125
fpga/tb/az80/control_pins_n.v
Normal file
125
fpga/tb/az80/control_pins_n.v
Normal file
@ -0,0 +1,125 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sun Nov 16 23:06:14 2014"
|
||||
|
||||
module control_pins_n(
|
||||
busack,
|
||||
CPUCLK,
|
||||
pin_control_oe,
|
||||
in_halt,
|
||||
pin_nWAIT,
|
||||
pin_nBUSRQ,
|
||||
pin_nINT,
|
||||
pin_nNMI,
|
||||
pin_nRESET,
|
||||
nM1_out,
|
||||
nRFSH_out,
|
||||
nRD_out,
|
||||
nWR_out,
|
||||
nIORQ_out,
|
||||
nMREQ_out,
|
||||
nmi,
|
||||
busrq,
|
||||
clk,
|
||||
intr,
|
||||
mwait,
|
||||
reset_in,
|
||||
pin_nM1,
|
||||
pin_nMREQ,
|
||||
pin_nIORQ,
|
||||
pin_nRD,
|
||||
pin_nWR,
|
||||
pin_nRFSH,
|
||||
pin_nHALT,
|
||||
pin_nBUSACK
|
||||
);
|
||||
|
||||
|
||||
input wire busack;
|
||||
input wire CPUCLK;
|
||||
input wire pin_control_oe;
|
||||
input wire in_halt;
|
||||
input wire pin_nWAIT;
|
||||
input wire pin_nBUSRQ;
|
||||
input wire pin_nINT;
|
||||
input wire pin_nNMI;
|
||||
input wire pin_nRESET;
|
||||
input wire nM1_out;
|
||||
input wire nRFSH_out;
|
||||
input wire nRD_out;
|
||||
input wire nWR_out;
|
||||
input wire nIORQ_out;
|
||||
input wire nMREQ_out;
|
||||
output wire nmi;
|
||||
output wire busrq;
|
||||
output wire clk;
|
||||
output wire intr;
|
||||
output wire mwait;
|
||||
output wire reset_in;
|
||||
output wire pin_nM1;
|
||||
output wire pin_nMREQ;
|
||||
output wire pin_nIORQ;
|
||||
output wire pin_nRD;
|
||||
output wire pin_nWR;
|
||||
output wire pin_nRFSH;
|
||||
output wire pin_nHALT;
|
||||
output wire pin_nBUSACK;
|
||||
|
||||
|
||||
assign clk = CPUCLK;
|
||||
assign pin_nM1 = nM1_out;
|
||||
assign pin_nRFSH = nRFSH_out;
|
||||
|
||||
|
||||
|
||||
assign pin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz;
|
||||
|
||||
assign pin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz;
|
||||
|
||||
assign pin_nRD = pin_control_oe ? nRD_out : 1'bz;
|
||||
|
||||
assign pin_nWR = pin_control_oe ? nWR_out : 1'bz;
|
||||
|
||||
assign busrq = ~pin_nBUSRQ;
|
||||
|
||||
assign pin_nHALT = ~in_halt;
|
||||
|
||||
assign mwait = ~pin_nWAIT;
|
||||
|
||||
assign pin_nBUSACK = ~busack;
|
||||
|
||||
assign intr = ~pin_nINT;
|
||||
|
||||
assign nmi = ~pin_nNMI;
|
||||
|
||||
assign reset_in = ~pin_nRESET;
|
||||
|
||||
|
||||
endmodule
|
||||
85
fpga/tb/az80/core.vh
Normal file
85
fpga/tb/az80/core.vh
Normal file
@ -0,0 +1,85 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
//============================================================================
|
||||
// A-Z80 core, instantiates and connects all internal blocks.
|
||||
//
|
||||
// This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing
|
||||
// interface binding and direct (no interface) binding.
|
||||
//============================================================================
|
||||
|
||||
// Include a list of top-level signal wires
|
||||
`include "globals.vh"
|
||||
|
||||
// Specific to simulation, some modules in the schematics need to be pre-initialized
|
||||
// to avoid starting simulations with unknown values in selected flip flops.
|
||||
reg fpga_reset = 1;
|
||||
always @(posedge clk)
|
||||
begin
|
||||
fpga_reset <= 0;
|
||||
end
|
||||
|
||||
// Define internal data bus partitions segmented by data bus switches
|
||||
wire [7:0] db0; // Segment connecting data pins and IR
|
||||
wire [7:0] db1; // Segment leading to the ALU
|
||||
wire [7:0] db2; // Segment with msb part of the register address-side interface
|
||||
|
||||
wire [7:0] db_hi_as; // Register file data bus segment high byte
|
||||
wire [7:0] db_lo_as; // Register file data bus segment low byte
|
||||
|
||||
wire [6:0] prefix; // Instruction decode PLA prefix bitfield
|
||||
assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
|
||||
|
||||
wire nM1_int; // External pins timing control
|
||||
assign nM1_int = !(setM1 | (fFetch & T1));
|
||||
|
||||
`include "coremodules.vh"
|
||||
|
||||
// Data path within the CPU in various forms, ending with data pins
|
||||
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
|
||||
|
||||
// Data switch SW1 with the data mask
|
||||
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
|
||||
|
||||
/* This SystemVerilog-style code is kept for future reference
|
||||
// Control block
|
||||
clk_delay clk_delay_( .* );
|
||||
decode_state decode_state_( .* );
|
||||
execute execute_( .* );
|
||||
interrupts interrupts_( .*, .db(db0[4:3]) );
|
||||
ir ir_( .*, .db(db0[7:0]) );
|
||||
pin_control pin_control_( .* );
|
||||
pla_decode pla_decode_( .* );
|
||||
resets resets_( .* );
|
||||
sequencer sequencer_( .* );
|
||||
|
||||
// ALU and ALU control, including the flags
|
||||
alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
|
||||
alu_select alu_select_( .* );
|
||||
alu_flags alu_flags_( .*, .db(db1[7:0]) );
|
||||
alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
|
||||
|
||||
// Register file and register control
|
||||
reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
|
||||
reg_control reg_control_( .* );
|
||||
|
||||
// Address latch and the incrementer
|
||||
address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
|
||||
|
||||
// Misc bus
|
||||
bus_control bus_control_( .*, .db(db0[7:0]) );
|
||||
bus_switch bus_switch_( .* );
|
||||
|
||||
// Timing control of the external pins
|
||||
memory_ifc memory_ifc_( .* );
|
||||
*/
|
||||
579
fpga/tb/az80/coremodules.vh
Normal file
579
fpga/tb/az80/coremodules.vh
Normal file
@ -0,0 +1,579 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Automatically generated by gencoremodules.py
|
||||
|
||||
clk_delay clk_delay_(
|
||||
.clk (clk),
|
||||
.in_intr (in_intr),
|
||||
.nreset (nreset),
|
||||
.T1 (T1),
|
||||
.latch_wait (latch_wait),
|
||||
.mwait (mwait),
|
||||
.M1 (M1),
|
||||
.busrq (busrq),
|
||||
.setM1 (setM1),
|
||||
.hold_clk_iorq (hold_clk_iorq),
|
||||
.hold_clk_wait (hold_clk_wait),
|
||||
.iorq_Tw (iorq_Tw),
|
||||
.busack (busack),
|
||||
.pin_control_oe (pin_control_oe),
|
||||
.hold_clk_busrq (hold_clk_busrq),
|
||||
.nhold_clk_wait (nhold_clk_wait)
|
||||
);
|
||||
|
||||
decode_state decode_state_(
|
||||
.ctl_state_iy_set (ctl_state_iy_set),
|
||||
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
|
||||
.ctl_state_ixiy_we (ctl_state_ixiy_we),
|
||||
.ctl_state_halt_set (ctl_state_halt_set),
|
||||
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
|
||||
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
|
||||
.ctl_state_alu (ctl_state_alu),
|
||||
.clk (clk),
|
||||
.address_is_1 (address_is_1),
|
||||
.ctl_repeat_we (ctl_repeat_we),
|
||||
.in_intr (in_intr),
|
||||
.in_nmi (in_nmi),
|
||||
.nreset (nreset),
|
||||
.ctl_state_tbl_we (ctl_state_tbl_we),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.in_halt (in_halt),
|
||||
.table_cb (table_cb),
|
||||
.table_ed (table_ed),
|
||||
.table_xx (table_xx),
|
||||
.use_ix (use_ix),
|
||||
.use_ixiy (use_ixiy),
|
||||
.in_alu (in_alu),
|
||||
.repeat_en (repeat_en)
|
||||
);
|
||||
|
||||
execute execute_(
|
||||
.ctl_state_iy_set (ctl_state_iy_set),
|
||||
.ctl_state_ixiy_clr (ctl_state_ixiy_clr),
|
||||
.ctl_state_ixiy_we (ctl_state_ixiy_we),
|
||||
.ctl_state_halt_set (ctl_state_halt_set),
|
||||
.ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),
|
||||
.ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),
|
||||
.ctl_state_alu (ctl_state_alu),
|
||||
.ctl_repeat_we (ctl_repeat_we),
|
||||
.ctl_state_tbl_we (ctl_state_tbl_we),
|
||||
.ctl_iff1_iff2 (ctl_iff1_iff2),
|
||||
.ctl_iffx_we (ctl_iffx_we),
|
||||
.ctl_iffx_bit (ctl_iffx_bit),
|
||||
.ctl_im_we (ctl_im_we),
|
||||
.ctl_no_ints (ctl_no_ints),
|
||||
.ctl_ir_we (ctl_ir_we),
|
||||
.ctl_mRead (ctl_mRead),
|
||||
.ctl_mWrite (ctl_mWrite),
|
||||
.ctl_iorw (ctl_iorw),
|
||||
.ctl_shift_en (ctl_shift_en),
|
||||
.ctl_daa_oe (ctl_daa_oe),
|
||||
.ctl_alu_op_low (ctl_alu_op_low),
|
||||
.ctl_cond_short (ctl_cond_short),
|
||||
.ctl_alu_core_hf (ctl_alu_core_hf),
|
||||
.ctl_eval_cond (ctl_eval_cond),
|
||||
.ctl_66_oe (ctl_66_oe),
|
||||
.ctl_pf_sel (ctl_pf_sel),
|
||||
.ctl_alu_oe (ctl_alu_oe),
|
||||
.ctl_alu_shift_oe (ctl_alu_shift_oe),
|
||||
.ctl_alu_op2_oe (ctl_alu_op2_oe),
|
||||
.ctl_alu_res_oe (ctl_alu_res_oe),
|
||||
.ctl_alu_op1_oe (ctl_alu_op1_oe),
|
||||
.ctl_alu_bs_oe (ctl_alu_bs_oe),
|
||||
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
|
||||
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
|
||||
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
|
||||
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
|
||||
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
|
||||
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
|
||||
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
|
||||
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
|
||||
.ctl_alu_core_R (ctl_alu_core_R),
|
||||
.ctl_alu_core_V (ctl_alu_core_V),
|
||||
.ctl_alu_core_S (ctl_alu_core_S),
|
||||
.ctl_flags_oe (ctl_flags_oe),
|
||||
.ctl_flags_bus (ctl_flags_bus),
|
||||
.ctl_flags_alu (ctl_flags_alu),
|
||||
.ctl_flags_nf_set (ctl_flags_nf_set),
|
||||
.ctl_flags_cf_set (ctl_flags_cf_set),
|
||||
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
|
||||
.ctl_flags_cf_we (ctl_flags_cf_we),
|
||||
.ctl_flags_sz_we (ctl_flags_sz_we),
|
||||
.ctl_flags_xy_we (ctl_flags_xy_we),
|
||||
.ctl_flags_hf_we (ctl_flags_hf_we),
|
||||
.ctl_flags_pf_we (ctl_flags_pf_we),
|
||||
.ctl_flags_nf_we (ctl_flags_nf_we),
|
||||
.ctl_flags_cf2_we (ctl_flags_cf2_we),
|
||||
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
|
||||
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
|
||||
.ctl_flags_hf2_we (ctl_flags_hf2_we),
|
||||
.ctl_flags_nf_clr (ctl_flags_nf_clr),
|
||||
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
|
||||
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
|
||||
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
|
||||
.ctl_sw_4u (ctl_sw_4u),
|
||||
.ctl_reg_in_hi (ctl_reg_in_hi),
|
||||
.ctl_reg_in_lo (ctl_reg_in_lo),
|
||||
.ctl_reg_out_lo (ctl_reg_out_lo),
|
||||
.ctl_reg_out_hi (ctl_reg_out_hi),
|
||||
.ctl_reg_exx (ctl_reg_exx),
|
||||
.ctl_reg_ex_af (ctl_reg_ex_af),
|
||||
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
|
||||
.ctl_reg_use_sp (ctl_reg_use_sp),
|
||||
.ctl_reg_sel_pc (ctl_reg_sel_pc),
|
||||
.ctl_reg_sel_ir (ctl_reg_sel_ir),
|
||||
.ctl_reg_sel_wz (ctl_reg_sel_wz),
|
||||
.ctl_reg_gp_we (ctl_reg_gp_we),
|
||||
.ctl_reg_not_pc (ctl_reg_not_pc),
|
||||
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
|
||||
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
|
||||
.ctl_reg_sys_we (ctl_reg_sys_we),
|
||||
.ctl_sw_4d (ctl_sw_4d),
|
||||
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
|
||||
.ctl_reg_gp_sel (ctl_reg_gp_sel),
|
||||
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
|
||||
.ctl_inc_cy (ctl_inc_cy),
|
||||
.ctl_inc_dec (ctl_inc_dec),
|
||||
.ctl_al_we (ctl_al_we),
|
||||
.ctl_inc_limit6 (ctl_inc_limit6),
|
||||
.ctl_bus_inc_oe (ctl_bus_inc_oe),
|
||||
.ctl_apin_mux (ctl_apin_mux),
|
||||
.ctl_apin_mux2 (ctl_apin_mux2),
|
||||
.ctl_bus_ff_oe (ctl_bus_ff_oe),
|
||||
.ctl_bus_zero_oe (ctl_bus_zero_oe),
|
||||
.ctl_sw_1u (ctl_sw_1u),
|
||||
.ctl_sw_1d (ctl_sw_1d),
|
||||
.ctl_sw_2u (ctl_sw_2u),
|
||||
.ctl_sw_2d (ctl_sw_2d),
|
||||
.ctl_sw_mask543_en (ctl_sw_mask543_en),
|
||||
.ctl_bus_db_we (ctl_bus_db_we),
|
||||
.ctl_bus_db_oe (ctl_bus_db_oe),
|
||||
.nextM (nextM),
|
||||
.setM1 (setM1),
|
||||
.fFetch (fFetch),
|
||||
.fMRead (fMRead),
|
||||
.fMWrite (fMWrite),
|
||||
.fIORead (fIORead),
|
||||
.fIOWrite (fIOWrite),
|
||||
.pla (pla),
|
||||
.in_intr (in_intr),
|
||||
.in_nmi (in_nmi),
|
||||
.in_halt (in_halt),
|
||||
.im1 (im1),
|
||||
.im2 (im2),
|
||||
.use_ixiy (use_ixiy),
|
||||
.flags_cond_true (flags_cond_true),
|
||||
.repeat_en (repeat_en),
|
||||
.flags_zf (flags_zf),
|
||||
.flags_nf (flags_nf),
|
||||
.flags_sf (flags_sf),
|
||||
.flags_cf (flags_cf),
|
||||
.M1 (M1),
|
||||
.M2 (M2),
|
||||
.M3 (M3),
|
||||
.M4 (M4),
|
||||
.M5 (M5),
|
||||
.T1 (T1),
|
||||
.T2 (T2),
|
||||
.T3 (T3),
|
||||
.T4 (T4),
|
||||
.T5 (T5),
|
||||
.T6 (T6)
|
||||
);
|
||||
|
||||
interrupts interrupts_(
|
||||
.ctl_iff1_iff2 (ctl_iff1_iff2),
|
||||
.nmi (nmi),
|
||||
.setM1 (setM1),
|
||||
.intr (intr),
|
||||
.ctl_iffx_we (ctl_iffx_we),
|
||||
.ctl_iffx_bit (ctl_iffx_bit),
|
||||
.ctl_im_we (ctl_im_we),
|
||||
.clk (clk),
|
||||
.ctl_no_ints (ctl_no_ints),
|
||||
.nreset (nreset),
|
||||
.db (db0[4:3]),
|
||||
.iff2 (iff2),
|
||||
.im1 (im1),
|
||||
.im2 (im2),
|
||||
.in_nmi (in_nmi),
|
||||
.in_intr (in_intr)
|
||||
);
|
||||
|
||||
ir ir_(
|
||||
.ctl_ir_we (ctl_ir_we),
|
||||
.clk (clk),
|
||||
.nreset (nreset),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.db (db0[7:0]),
|
||||
.opcode (opcode)
|
||||
);
|
||||
|
||||
pin_control pin_control_(
|
||||
.fFetch (fFetch),
|
||||
.fMRead (fMRead),
|
||||
.fMWrite (fMWrite),
|
||||
.fIORead (fIORead),
|
||||
.fIOWrite (fIOWrite),
|
||||
.T1 (T1),
|
||||
.T2 (T2),
|
||||
.T3 (T3),
|
||||
.T4 (T4),
|
||||
.bus_ab_pin_we (bus_ab_pin_we),
|
||||
.bus_db_pin_oe (bus_db_pin_oe),
|
||||
.bus_db_pin_re (bus_db_pin_re)
|
||||
);
|
||||
|
||||
pla_decode pla_decode_(
|
||||
.prefix (prefix),
|
||||
.opcode (opcode),
|
||||
.pla (pla)
|
||||
);
|
||||
|
||||
resets resets_(
|
||||
.reset_in (reset_in),
|
||||
.clk (clk),
|
||||
.M1 (M1),
|
||||
.T2 (T2),
|
||||
.fpga_reset (fpga_reset),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.clrpc (clrpc),
|
||||
.nreset (nreset)
|
||||
);
|
||||
|
||||
memory_ifc memory_ifc_(
|
||||
.clk (clk),
|
||||
.nM1_int (nM1_int),
|
||||
.ctl_mRead (ctl_mRead),
|
||||
.ctl_mWrite (ctl_mWrite),
|
||||
.in_intr (in_intr),
|
||||
.nreset (nreset),
|
||||
.fIORead (fIORead),
|
||||
.fIOWrite (fIOWrite),
|
||||
.setM1 (setM1),
|
||||
.ctl_iorw (ctl_iorw),
|
||||
.timings_en (timings_en),
|
||||
.iorq_Tw (iorq_Tw),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.nM1_out (nM1_out),
|
||||
.nRFSH_out (nRFSH_out),
|
||||
.nMREQ_out (nMREQ_out),
|
||||
.nRD_out (nRD_out),
|
||||
.nWR_out (nWR_out),
|
||||
.nIORQ_out (nIORQ_out),
|
||||
.latch_wait (latch_wait),
|
||||
.wait_m1 (wait_m1)
|
||||
);
|
||||
|
||||
sequencer sequencer_(
|
||||
.clk (clk),
|
||||
.nextM (nextM),
|
||||
.setM1 (setM1),
|
||||
.nreset (nreset),
|
||||
.hold_clk_iorq (hold_clk_iorq),
|
||||
.hold_clk_wait (hold_clk_wait),
|
||||
.hold_clk_busrq (hold_clk_busrq),
|
||||
.M1 (M1),
|
||||
.M2 (M2),
|
||||
.M3 (M3),
|
||||
.M4 (M4),
|
||||
.M5 (M5),
|
||||
.T1 (T1),
|
||||
.T2 (T2),
|
||||
.T3 (T3),
|
||||
.T4 (T4),
|
||||
.T5 (T5),
|
||||
.T6 (T6),
|
||||
.timings_en (timings_en)
|
||||
);
|
||||
|
||||
alu_control alu_control_(
|
||||
.alu_shift_db0 (alu_shift_db0),
|
||||
.alu_shift_db7 (alu_shift_db7),
|
||||
.ctl_shift_en (ctl_shift_en),
|
||||
.alu_low_gt_9 (alu_low_gt_9),
|
||||
.alu_high_gt_9 (alu_high_gt_9),
|
||||
.alu_high_eq_9 (alu_high_eq_9),
|
||||
.ctl_daa_oe (ctl_daa_oe),
|
||||
.ctl_alu_op_low (ctl_alu_op_low),
|
||||
.alu_parity_out (alu_parity_out),
|
||||
.flags_cf (flags_cf),
|
||||
.flags_zf (flags_zf),
|
||||
.flags_pf (flags_pf),
|
||||
.flags_sf (flags_sf),
|
||||
.ctl_cond_short (ctl_cond_short),
|
||||
.alu_vf_out (alu_vf_out),
|
||||
.iff2 (iff2),
|
||||
.ctl_alu_core_hf (ctl_alu_core_hf),
|
||||
.ctl_eval_cond (ctl_eval_cond),
|
||||
.repeat_en (repeat_en),
|
||||
.flags_cf_latch (flags_cf_latch),
|
||||
.flags_hf2 (flags_hf2),
|
||||
.flags_hf (flags_hf),
|
||||
.ctl_66_oe (ctl_66_oe),
|
||||
.clk (clk),
|
||||
.ctl_pf_sel (ctl_pf_sel),
|
||||
.op543 ({pla[104],pla[103],pla[102]}),
|
||||
.alu_shift_in (alu_shift_in),
|
||||
.alu_shift_right (alu_shift_right),
|
||||
.alu_shift_left (alu_shift_left),
|
||||
.shift_cf_out (shift_cf_out),
|
||||
.alu_parity_in (alu_parity_in),
|
||||
.flags_cond_true (flags_cond_true),
|
||||
.daa_cf_out (daa_cf_out),
|
||||
.pf_sel (pf_sel),
|
||||
.alu_op_low (alu_op_low),
|
||||
.alu_core_cf_in (alu_core_cf_in),
|
||||
.db (db1[7:0])
|
||||
);
|
||||
|
||||
alu_select alu_select_(
|
||||
.ctl_alu_oe (ctl_alu_oe),
|
||||
.ctl_alu_shift_oe (ctl_alu_shift_oe),
|
||||
.ctl_alu_op2_oe (ctl_alu_op2_oe),
|
||||
.ctl_alu_res_oe (ctl_alu_res_oe),
|
||||
.ctl_alu_op1_oe (ctl_alu_op1_oe),
|
||||
.ctl_alu_bs_oe (ctl_alu_bs_oe),
|
||||
.ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),
|
||||
.ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),
|
||||
.ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),
|
||||
.ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),
|
||||
.ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),
|
||||
.ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),
|
||||
.ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),
|
||||
.ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),
|
||||
.ctl_alu_core_R (ctl_alu_core_R),
|
||||
.ctl_alu_core_V (ctl_alu_core_V),
|
||||
.ctl_alu_core_S (ctl_alu_core_S),
|
||||
.alu_oe (alu_oe),
|
||||
.alu_shift_oe (alu_shift_oe),
|
||||
.alu_op2_oe (alu_op2_oe),
|
||||
.alu_res_oe (alu_res_oe),
|
||||
.alu_op1_oe (alu_op1_oe),
|
||||
.alu_bs_oe (alu_bs_oe),
|
||||
.alu_op1_sel_bus (alu_op1_sel_bus),
|
||||
.alu_op1_sel_low (alu_op1_sel_low),
|
||||
.alu_op1_sel_zero (alu_op1_sel_zero),
|
||||
.alu_op2_sel_zero (alu_op2_sel_zero),
|
||||
.alu_op2_sel_bus (alu_op2_sel_bus),
|
||||
.alu_op2_sel_lq (alu_op2_sel_lq),
|
||||
.alu_sel_op2_neg (alu_sel_op2_neg),
|
||||
.alu_sel_op2_high (alu_sel_op2_high),
|
||||
.alu_core_R (alu_core_R),
|
||||
.alu_core_V (alu_core_V),
|
||||
.alu_core_S (alu_core_S)
|
||||
);
|
||||
|
||||
alu_flags alu_flags_(
|
||||
.ctl_flags_oe (ctl_flags_oe),
|
||||
.ctl_flags_bus (ctl_flags_bus),
|
||||
.ctl_flags_alu (ctl_flags_alu),
|
||||
.alu_sf_out (alu_sf_out),
|
||||
.alu_yf_out (alu_yf_out),
|
||||
.alu_xf_out (alu_xf_out),
|
||||
.ctl_flags_nf_set (ctl_flags_nf_set),
|
||||
.alu_zero (alu_zero),
|
||||
.shift_cf_out (shift_cf_out),
|
||||
.alu_core_cf_out (alu_core_cf_out),
|
||||
.daa_cf_out (daa_cf_out),
|
||||
.ctl_flags_cf_set (ctl_flags_cf_set),
|
||||
.ctl_flags_cf_cpl (ctl_flags_cf_cpl),
|
||||
.pf_sel (pf_sel),
|
||||
.ctl_flags_cf_we (ctl_flags_cf_we),
|
||||
.ctl_flags_sz_we (ctl_flags_sz_we),
|
||||
.ctl_flags_xy_we (ctl_flags_xy_we),
|
||||
.ctl_flags_hf_we (ctl_flags_hf_we),
|
||||
.ctl_flags_pf_we (ctl_flags_pf_we),
|
||||
.ctl_flags_nf_we (ctl_flags_nf_we),
|
||||
.ctl_flags_cf2_we (ctl_flags_cf2_we),
|
||||
.ctl_flags_hf_cpl (ctl_flags_hf_cpl),
|
||||
.ctl_flags_use_cf2 (ctl_flags_use_cf2),
|
||||
.ctl_flags_hf2_we (ctl_flags_hf2_we),
|
||||
.ctl_flags_nf_clr (ctl_flags_nf_clr),
|
||||
.ctl_alu_zero_16bit (ctl_alu_zero_16bit),
|
||||
.clk (clk),
|
||||
.ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),
|
||||
.ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.flags_sf (flags_sf),
|
||||
.flags_zf (flags_zf),
|
||||
.flags_hf (flags_hf),
|
||||
.flags_pf (flags_pf),
|
||||
.flags_cf (flags_cf),
|
||||
.flags_nf (flags_nf),
|
||||
.flags_cf_latch (flags_cf_latch),
|
||||
.flags_hf2 (flags_hf2),
|
||||
.db (db1[7:0])
|
||||
);
|
||||
|
||||
alu alu_(
|
||||
.alu_core_R (alu_core_R),
|
||||
.alu_core_V (alu_core_V),
|
||||
.alu_core_S (alu_core_S),
|
||||
.alu_bs_oe (alu_bs_oe),
|
||||
.alu_parity_in (alu_parity_in),
|
||||
.alu_oe (alu_oe),
|
||||
.alu_shift_oe (alu_shift_oe),
|
||||
.alu_core_cf_in (alu_core_cf_in),
|
||||
.alu_op2_oe (alu_op2_oe),
|
||||
.alu_op1_oe (alu_op1_oe),
|
||||
.alu_res_oe (alu_res_oe),
|
||||
.alu_op1_sel_low (alu_op1_sel_low),
|
||||
.alu_op1_sel_zero (alu_op1_sel_zero),
|
||||
.alu_op1_sel_bus (alu_op1_sel_bus),
|
||||
.alu_op2_sel_zero (alu_op2_sel_zero),
|
||||
.alu_op2_sel_bus (alu_op2_sel_bus),
|
||||
.alu_op2_sel_lq (alu_op2_sel_lq),
|
||||
.alu_op_low (alu_op_low),
|
||||
.alu_shift_in (alu_shift_in),
|
||||
.alu_sel_op2_neg (alu_sel_op2_neg),
|
||||
.alu_sel_op2_high (alu_sel_op2_high),
|
||||
.alu_shift_left (alu_shift_left),
|
||||
.alu_shift_right (alu_shift_right),
|
||||
.clk (clk),
|
||||
.bsel (db0[5:3]),
|
||||
.alu_zero (alu_zero),
|
||||
.alu_parity_out (alu_parity_out),
|
||||
.alu_high_eq_9 (alu_high_eq_9),
|
||||
.alu_high_gt_9 (alu_high_gt_9),
|
||||
.alu_low_gt_9 (alu_low_gt_9),
|
||||
.alu_shift_db0 (alu_shift_db0),
|
||||
.alu_shift_db7 (alu_shift_db7),
|
||||
.alu_core_cf_out (alu_core_cf_out),
|
||||
.alu_sf_out (alu_sf_out),
|
||||
.alu_yf_out (alu_yf_out),
|
||||
.alu_xf_out (alu_xf_out),
|
||||
.alu_vf_out (alu_vf_out),
|
||||
.db (db2[7:0]),
|
||||
.test_db_high (test_db_high),
|
||||
.test_db_low (test_db_low)
|
||||
);
|
||||
|
||||
reg_file reg_file_(
|
||||
.reg_sel_sys_lo (reg_sel_sys_lo),
|
||||
.reg_sel_gp_lo (reg_sel_gp_lo),
|
||||
.reg_sel_sys_hi (reg_sel_sys_hi),
|
||||
.reg_sel_gp_hi (reg_sel_gp_hi),
|
||||
.reg_sel_ir (reg_sel_ir),
|
||||
.reg_sel_pc (reg_sel_pc),
|
||||
.ctl_sw_4u (ctl_sw_4u),
|
||||
.reg_sel_wz (reg_sel_wz),
|
||||
.reg_sel_sp (reg_sel_sp),
|
||||
.reg_sel_iy (reg_sel_iy),
|
||||
.reg_sel_ix (reg_sel_ix),
|
||||
.reg_sel_hl2 (reg_sel_hl2),
|
||||
.reg_sel_hl (reg_sel_hl),
|
||||
.reg_sel_de2 (reg_sel_de2),
|
||||
.reg_sel_de (reg_sel_de),
|
||||
.reg_sel_bc2 (reg_sel_bc2),
|
||||
.reg_sel_bc (reg_sel_bc),
|
||||
.reg_sel_af2 (reg_sel_af2),
|
||||
.reg_sel_af (reg_sel_af),
|
||||
.reg_gp_we (reg_gp_we),
|
||||
.reg_sys_we_lo (reg_sys_we_lo),
|
||||
.reg_sys_we_hi (reg_sys_we_hi),
|
||||
.ctl_reg_in_hi (ctl_reg_in_hi),
|
||||
.ctl_reg_in_lo (ctl_reg_in_lo),
|
||||
.ctl_reg_out_lo (ctl_reg_out_lo),
|
||||
.ctl_reg_out_hi (ctl_reg_out_hi),
|
||||
.clk (clk),
|
||||
.reg_sw_4d_lo (reg_sw_4d_lo),
|
||||
.reg_sw_4d_hi (reg_sw_4d_hi),
|
||||
.db_hi_as (db_hi_as[7:0]),
|
||||
.db_hi_ds (db2[7:0]),
|
||||
.db_lo_as (db_lo_as[7:0]),
|
||||
.db_lo_ds (db1[7:0])
|
||||
);
|
||||
|
||||
reg_control reg_control_(
|
||||
.ctl_reg_exx (ctl_reg_exx),
|
||||
.ctl_reg_ex_af (ctl_reg_ex_af),
|
||||
.ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),
|
||||
.ctl_reg_use_sp (ctl_reg_use_sp),
|
||||
.nreset (nreset),
|
||||
.ctl_reg_sel_pc (ctl_reg_sel_pc),
|
||||
.ctl_reg_sel_ir (ctl_reg_sel_ir),
|
||||
.ctl_reg_sel_wz (ctl_reg_sel_wz),
|
||||
.ctl_reg_gp_we (ctl_reg_gp_we),
|
||||
.ctl_reg_not_pc (ctl_reg_not_pc),
|
||||
.use_ixiy (use_ixiy),
|
||||
.use_ix (use_ix),
|
||||
.ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),
|
||||
.ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),
|
||||
.ctl_reg_sys_we (ctl_reg_sys_we),
|
||||
.clk (clk),
|
||||
.ctl_sw_4d (ctl_sw_4d),
|
||||
.nhold_clk_wait (nhold_clk_wait),
|
||||
.ctl_reg_gp_hilo (ctl_reg_gp_hilo),
|
||||
.ctl_reg_gp_sel (ctl_reg_gp_sel),
|
||||
.ctl_reg_sys_hilo (ctl_reg_sys_hilo),
|
||||
.reg_sel_bc (reg_sel_bc),
|
||||
.reg_sel_bc2 (reg_sel_bc2),
|
||||
.reg_sel_ix (reg_sel_ix),
|
||||
.reg_sel_iy (reg_sel_iy),
|
||||
.reg_sel_de (reg_sel_de),
|
||||
.reg_sel_hl (reg_sel_hl),
|
||||
.reg_sel_de2 (reg_sel_de2),
|
||||
.reg_sel_hl2 (reg_sel_hl2),
|
||||
.reg_sel_af (reg_sel_af),
|
||||
.reg_sel_af2 (reg_sel_af2),
|
||||
.reg_sel_wz (reg_sel_wz),
|
||||
.reg_sel_pc (reg_sel_pc),
|
||||
.reg_sel_ir (reg_sel_ir),
|
||||
.reg_sel_sp (reg_sel_sp),
|
||||
.reg_sel_gp_hi (reg_sel_gp_hi),
|
||||
.reg_sel_gp_lo (reg_sel_gp_lo),
|
||||
.reg_sel_sys_lo (reg_sel_sys_lo),
|
||||
.reg_sel_sys_hi (reg_sel_sys_hi),
|
||||
.reg_gp_we (reg_gp_we),
|
||||
.reg_sys_we_lo (reg_sys_we_lo),
|
||||
.reg_sys_we_hi (reg_sys_we_hi),
|
||||
.reg_sw_4d_lo (reg_sw_4d_lo),
|
||||
.reg_sw_4d_hi (reg_sw_4d_hi)
|
||||
);
|
||||
|
||||
address_latch address_latch_(
|
||||
.ctl_inc_cy (ctl_inc_cy),
|
||||
.ctl_inc_dec (ctl_inc_dec),
|
||||
.ctl_al_we (ctl_al_we),
|
||||
.ctl_inc_limit6 (ctl_inc_limit6),
|
||||
.ctl_bus_inc_oe (ctl_bus_inc_oe),
|
||||
.clk (clk),
|
||||
.ctl_apin_mux (ctl_apin_mux),
|
||||
.ctl_apin_mux2 (ctl_apin_mux2),
|
||||
.clrpc (clrpc),
|
||||
.nreset (nreset),
|
||||
.address_is_1 (address_is_1),
|
||||
.abus ({db_hi_as[7:0], db_lo_as[7:0]}),
|
||||
.address (address)
|
||||
);
|
||||
|
||||
bus_control bus_control_(
|
||||
.ctl_bus_ff_oe (ctl_bus_ff_oe),
|
||||
.ctl_bus_zero_oe (ctl_bus_zero_oe),
|
||||
.db (db0[7:0])
|
||||
);
|
||||
|
||||
bus_switch bus_switch_(
|
||||
.ctl_sw_1u (ctl_sw_1u),
|
||||
.ctl_sw_1d (ctl_sw_1d),
|
||||
.ctl_sw_2u (ctl_sw_2u),
|
||||
.ctl_sw_2d (ctl_sw_2d),
|
||||
.ctl_sw_mask543_en (ctl_sw_mask543_en),
|
||||
.bus_sw_1u (bus_sw_1u),
|
||||
.bus_sw_1d (bus_sw_1d),
|
||||
.bus_sw_2u (bus_sw_2u),
|
||||
.bus_sw_2d (bus_sw_2d),
|
||||
.bus_sw_mask543_en (bus_sw_mask543_en)
|
||||
);
|
||||
99
fpga/tb/az80/data_pins.v
Normal file
99
fpga/tb/az80/data_pins.v
Normal file
@ -0,0 +1,99 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Thu Nov 06 23:28:26 2014"
|
||||
|
||||
module data_pins(
|
||||
bus_db_pin_oe,
|
||||
bus_db_pin_re,
|
||||
ctl_bus_db_we,
|
||||
clk,
|
||||
ctl_bus_db_oe,
|
||||
D,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire bus_db_pin_oe;
|
||||
input wire bus_db_pin_re;
|
||||
input wire ctl_bus_db_we;
|
||||
input wire clk;
|
||||
input wire ctl_bus_db_oe;
|
||||
inout wire [7:0] D;
|
||||
inout wire [7:0] db;
|
||||
|
||||
reg [7:0] dout;
|
||||
wire [7:0] SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire [7:0] SYNTHESIZED_WIRE_3;
|
||||
wire [7:0] SYNTHESIZED_WIRE_4;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_1)
|
||||
begin
|
||||
if (SYNTHESIZED_WIRE_2)
|
||||
begin
|
||||
dout[7:0] <= SYNTHESIZED_WIRE_0[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;
|
||||
|
||||
assign db[7] = ctl_bus_db_oe ? dout[7] : 1'bz;
|
||||
assign db[6] = ctl_bus_db_oe ? dout[6] : 1'bz;
|
||||
assign db[5] = ctl_bus_db_oe ? dout[5] : 1'bz;
|
||||
assign db[4] = ctl_bus_db_oe ? dout[4] : 1'bz;
|
||||
assign db[3] = ctl_bus_db_oe ? dout[3] : 1'bz;
|
||||
assign db[2] = ctl_bus_db_oe ? dout[2] : 1'bz;
|
||||
assign db[1] = ctl_bus_db_oe ? dout[1] : 1'bz;
|
||||
assign db[0] = ctl_bus_db_oe ? dout[0] : 1'bz;
|
||||
|
||||
assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz;
|
||||
assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz;
|
||||
assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz;
|
||||
assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz;
|
||||
assign D[3] = bus_db_pin_oe ? dout[3] : 1'bz;
|
||||
assign D[2] = bus_db_pin_oe ? dout[2] : 1'bz;
|
||||
assign D[1] = bus_db_pin_oe ? dout[1] : 1'bz;
|
||||
assign D[0] = bus_db_pin_oe ? dout[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~clk;
|
||||
|
||||
|
||||
endmodule
|
||||
68
fpga/tb/az80/data_switch.v
Normal file
68
fpga/tb/az80/data_switch.v
Normal file
@ -0,0 +1,68 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:33:19 2014"
|
||||
|
||||
module data_switch(
|
||||
sw_up_en,
|
||||
sw_down_en,
|
||||
db_down,
|
||||
db_up
|
||||
);
|
||||
|
||||
|
||||
input wire sw_up_en;
|
||||
input wire sw_down_en;
|
||||
inout wire [7:0] db_down;
|
||||
inout wire [7:0] db_up;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
|
||||
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
|
||||
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
|
||||
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
|
||||
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
|
||||
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
|
||||
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
|
||||
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
|
||||
|
||||
assign db_down[7] = sw_down_en ? db_up[7] : 1'bz;
|
||||
assign db_down[6] = sw_down_en ? db_up[6] : 1'bz;
|
||||
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
|
||||
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
|
||||
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
|
||||
assign db_down[2] = sw_down_en ? db_up[2] : 1'bz;
|
||||
assign db_down[1] = sw_down_en ? db_up[1] : 1'bz;
|
||||
assign db_down[0] = sw_down_en ? db_up[0] : 1'bz;
|
||||
|
||||
|
||||
endmodule
|
||||
81
fpga/tb/az80/data_switch_mask.v
Normal file
81
fpga/tb/az80/data_switch_mask.v
Normal file
@ -0,0 +1,81 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:32:03 2014"
|
||||
|
||||
module data_switch_mask(
|
||||
sw_up_en,
|
||||
sw_down_en,
|
||||
sw_mask543_en,
|
||||
db_down,
|
||||
db_up
|
||||
);
|
||||
|
||||
|
||||
input wire sw_up_en;
|
||||
input wire sw_down_en;
|
||||
input wire sw_mask543_en;
|
||||
inout wire [7:0] db_down;
|
||||
inout wire [7:0] db_up;
|
||||
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire [1:0] SYNTHESIZED_WIRE_1;
|
||||
wire [2:0] SYNTHESIZED_WIRE_2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ~sw_mask543_en;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = db_up[7:6] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};
|
||||
|
||||
assign db_down[7] = sw_down_en ? SYNTHESIZED_WIRE_1[1] : 1'bz;
|
||||
assign db_down[6] = sw_down_en ? SYNTHESIZED_WIRE_1[0] : 1'bz;
|
||||
|
||||
assign db_down[2] = sw_down_en ? SYNTHESIZED_WIRE_2[2] : 1'bz;
|
||||
assign db_down[1] = sw_down_en ? SYNTHESIZED_WIRE_2[1] : 1'bz;
|
||||
assign db_down[0] = sw_down_en ? SYNTHESIZED_WIRE_2[0] : 1'bz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = db_up[2:0] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};
|
||||
|
||||
assign db_up[7] = sw_up_en ? db_down[7] : 1'bz;
|
||||
assign db_up[6] = sw_up_en ? db_down[6] : 1'bz;
|
||||
assign db_up[5] = sw_up_en ? db_down[5] : 1'bz;
|
||||
assign db_up[4] = sw_up_en ? db_down[4] : 1'bz;
|
||||
assign db_up[3] = sw_up_en ? db_down[3] : 1'bz;
|
||||
assign db_up[2] = sw_up_en ? db_down[2] : 1'bz;
|
||||
assign db_up[1] = sw_up_en ? db_down[1] : 1'bz;
|
||||
assign db_up[0] = sw_up_en ? db_down[0] : 1'bz;
|
||||
|
||||
assign db_down[5] = sw_down_en ? db_up[5] : 1'bz;
|
||||
assign db_down[4] = sw_down_en ? db_up[4] : 1'bz;
|
||||
assign db_down[3] = sw_down_en ? db_up[3] : 1'bz;
|
||||
|
||||
|
||||
endmodule
|
||||
195
fpga/tb/az80/decode_state.v
Normal file
195
fpga/tb/az80/decode_state.v
Normal file
@ -0,0 +1,195 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 08:55:35 2016"
|
||||
|
||||
module decode_state(
|
||||
ctl_state_iy_set,
|
||||
ctl_state_ixiy_clr,
|
||||
ctl_state_ixiy_we,
|
||||
ctl_state_halt_set,
|
||||
ctl_state_tbl_ed_set,
|
||||
ctl_state_tbl_cb_set,
|
||||
ctl_state_alu,
|
||||
clk,
|
||||
address_is_1,
|
||||
ctl_repeat_we,
|
||||
in_intr,
|
||||
in_nmi,
|
||||
nreset,
|
||||
ctl_state_tbl_we,
|
||||
nhold_clk_wait,
|
||||
in_halt,
|
||||
table_cb,
|
||||
table_ed,
|
||||
table_xx,
|
||||
use_ix,
|
||||
use_ixiy,
|
||||
in_alu,
|
||||
repeat_en
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_state_iy_set;
|
||||
input wire ctl_state_ixiy_clr;
|
||||
input wire ctl_state_ixiy_we;
|
||||
input wire ctl_state_halt_set;
|
||||
input wire ctl_state_tbl_ed_set;
|
||||
input wire ctl_state_tbl_cb_set;
|
||||
input wire ctl_state_alu;
|
||||
input wire clk;
|
||||
input wire address_is_1;
|
||||
input wire ctl_repeat_we;
|
||||
input wire in_intr;
|
||||
input wire in_nmi;
|
||||
input wire nreset;
|
||||
input wire ctl_state_tbl_we;
|
||||
input wire nhold_clk_wait;
|
||||
output reg in_halt;
|
||||
output wire table_cb;
|
||||
output wire table_ed;
|
||||
output wire table_xx;
|
||||
output wire use_ix;
|
||||
output wire use_ixiy;
|
||||
output wire in_alu;
|
||||
output wire repeat_en;
|
||||
|
||||
reg DFFE_instNonRep;
|
||||
reg DFFE_instIY1;
|
||||
reg DFFE_inst4;
|
||||
reg DFFE_instED;
|
||||
reg DFFE_instCB;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign in_alu = ctl_state_alu;
|
||||
assign table_cb = DFFE_instCB;
|
||||
assign table_ed = DFFE_instED;
|
||||
assign use_ix = DFFE_inst4;
|
||||
|
||||
|
||||
|
||||
assign repeat_en = ~DFFE_instNonRep;
|
||||
|
||||
assign use_ixiy = DFFE_instIY1 | DFFE_inst4;
|
||||
|
||||
assign table_xx = ~(DFFE_instED | DFFE_instCB);
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_inst4 <= 0;
|
||||
end
|
||||
else
|
||||
if (ctl_state_ixiy_we)
|
||||
begin
|
||||
DFFE_inst4 <= SYNTHESIZED_WIRE_0;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ctl_state_tbl_we & nhold_clk_wait;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = in_nmi | in_intr;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_instCB <= 0;
|
||||
end
|
||||
else
|
||||
if (SYNTHESIZED_WIRE_4)
|
||||
begin
|
||||
DFFE_instCB <= ctl_state_tbl_cb_set;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_instED <= 0;
|
||||
end
|
||||
else
|
||||
if (SYNTHESIZED_WIRE_4)
|
||||
begin
|
||||
DFFE_instED <= ctl_state_tbl_ed_set;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
in_halt <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
in_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_instIY1 <= 0;
|
||||
end
|
||||
else
|
||||
if (ctl_state_ixiy_we)
|
||||
begin
|
||||
DFFE_instIY1 <= ctl_state_iy_set;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_instNonRep <= 0;
|
||||
end
|
||||
else
|
||||
if (ctl_repeat_we)
|
||||
begin
|
||||
DFFE_instNonRep <= address_is_1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
3895
fpga/tb/az80/exec_matrix.vh
Normal file
3895
fpga/tb/az80/exec_matrix.vh
Normal file
File diff suppressed because it is too large
Load Diff
5825
fpga/tb/az80/exec_matrix_compiled.vh
Normal file
5825
fpga/tb/az80/exec_matrix_compiled.vh
Normal file
File diff suppressed because it is too large
Load Diff
140
fpga/tb/az80/exec_module.vh
Normal file
140
fpga/tb/az80/exec_module.vh
Normal file
@ -0,0 +1,140 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Automatically generated by genref.py
|
||||
|
||||
// Module: control/decode_state.v
|
||||
output reg ctl_state_iy_set,
|
||||
output reg ctl_state_ixiy_clr,
|
||||
output reg ctl_state_ixiy_we,
|
||||
output reg ctl_state_halt_set,
|
||||
output reg ctl_state_tbl_ed_set,
|
||||
output reg ctl_state_tbl_cb_set,
|
||||
output reg ctl_state_alu,
|
||||
output reg ctl_repeat_we,
|
||||
output reg ctl_state_tbl_we,
|
||||
|
||||
// Module: control/interrupts.v
|
||||
output reg ctl_iff1_iff2,
|
||||
output reg ctl_iffx_we,
|
||||
output reg ctl_iffx_bit,
|
||||
output reg ctl_im_we,
|
||||
output reg ctl_no_ints,
|
||||
|
||||
// Module: control/ir.v
|
||||
output reg ctl_ir_we,
|
||||
|
||||
// Module: control/memory_ifc.v
|
||||
output reg ctl_mRead,
|
||||
output reg ctl_mWrite,
|
||||
output reg ctl_iorw,
|
||||
|
||||
// Module: alu/alu_control.v
|
||||
output reg ctl_shift_en,
|
||||
output reg ctl_daa_oe,
|
||||
output reg ctl_alu_op_low,
|
||||
output reg ctl_cond_short,
|
||||
output reg ctl_alu_core_hf,
|
||||
output reg ctl_eval_cond,
|
||||
output reg ctl_66_oe,
|
||||
output reg [1:0] ctl_pf_sel,
|
||||
|
||||
// Module: alu/alu_select.v
|
||||
output reg ctl_alu_oe,
|
||||
output reg ctl_alu_shift_oe,
|
||||
output reg ctl_alu_op2_oe,
|
||||
output reg ctl_alu_res_oe,
|
||||
output reg ctl_alu_op1_oe,
|
||||
output reg ctl_alu_bs_oe,
|
||||
output reg ctl_alu_op1_sel_bus,
|
||||
output reg ctl_alu_op1_sel_low,
|
||||
output reg ctl_alu_op1_sel_zero,
|
||||
output reg ctl_alu_op2_sel_zero,
|
||||
output reg ctl_alu_op2_sel_bus,
|
||||
output reg ctl_alu_op2_sel_lq,
|
||||
output reg ctl_alu_sel_op2_neg,
|
||||
output reg ctl_alu_sel_op2_high,
|
||||
output reg ctl_alu_core_R,
|
||||
output reg ctl_alu_core_V,
|
||||
output reg ctl_alu_core_S,
|
||||
|
||||
// Module: alu/alu_flags.v
|
||||
output reg ctl_flags_oe,
|
||||
output reg ctl_flags_bus,
|
||||
output reg ctl_flags_alu,
|
||||
output reg ctl_flags_nf_set,
|
||||
output reg ctl_flags_cf_set,
|
||||
output reg ctl_flags_cf_cpl,
|
||||
output reg ctl_flags_cf_we,
|
||||
output reg ctl_flags_sz_we,
|
||||
output reg ctl_flags_xy_we,
|
||||
output reg ctl_flags_hf_we,
|
||||
output reg ctl_flags_pf_we,
|
||||
output reg ctl_flags_nf_we,
|
||||
output reg ctl_flags_cf2_we,
|
||||
output reg ctl_flags_hf_cpl,
|
||||
output reg ctl_flags_use_cf2,
|
||||
output reg ctl_flags_hf2_we,
|
||||
output reg ctl_flags_nf_clr,
|
||||
output reg ctl_alu_zero_16bit,
|
||||
output reg ctl_flags_cf2_sel_shift,
|
||||
output reg ctl_flags_cf2_sel_daa,
|
||||
|
||||
// Module: registers/reg_file.v
|
||||
output reg ctl_sw_4u,
|
||||
output reg ctl_reg_in_hi,
|
||||
output reg ctl_reg_in_lo,
|
||||
output reg ctl_reg_out_lo,
|
||||
output reg ctl_reg_out_hi,
|
||||
|
||||
// Module: registers/reg_control.v
|
||||
output reg ctl_reg_exx,
|
||||
output reg ctl_reg_ex_af,
|
||||
output reg ctl_reg_ex_de_hl,
|
||||
output reg ctl_reg_use_sp,
|
||||
output reg ctl_reg_sel_pc,
|
||||
output reg ctl_reg_sel_ir,
|
||||
output reg ctl_reg_sel_wz,
|
||||
output reg ctl_reg_gp_we,
|
||||
output reg ctl_reg_not_pc,
|
||||
output reg ctl_reg_sys_we_lo,
|
||||
output reg ctl_reg_sys_we_hi,
|
||||
output reg ctl_reg_sys_we,
|
||||
output reg ctl_sw_4d,
|
||||
output reg [1:0] ctl_reg_gp_hilo,
|
||||
output reg [1:0] ctl_reg_gp_sel,
|
||||
output reg [1:0] ctl_reg_sys_hilo,
|
||||
|
||||
// Module: bus/address_latch.v
|
||||
output reg ctl_inc_cy,
|
||||
output reg ctl_inc_dec,
|
||||
output reg ctl_al_we,
|
||||
output reg ctl_inc_limit6,
|
||||
output reg ctl_bus_inc_oe,
|
||||
output reg ctl_apin_mux,
|
||||
output reg ctl_apin_mux2,
|
||||
|
||||
// Module: bus/bus_control.v
|
||||
output reg ctl_bus_ff_oe,
|
||||
output reg ctl_bus_zero_oe,
|
||||
|
||||
// Module: bus/bus_switch.v
|
||||
output reg ctl_sw_1u,
|
||||
output reg ctl_sw_1d,
|
||||
output reg ctl_sw_2u,
|
||||
output reg ctl_sw_2d,
|
||||
output reg ctl_sw_mask543_en,
|
||||
|
||||
// Module: bus/data_pins.v
|
||||
output reg ctl_bus_db_we,
|
||||
output reg ctl_bus_db_oe,
|
||||
140
fpga/tb/az80/exec_zero.vh
Normal file
140
fpga/tb/az80/exec_zero.vh
Normal file
@ -0,0 +1,140 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Automatically generated by genref.py
|
||||
|
||||
// Module: control/decode_state.v
|
||||
ctl_state_iy_set = 0;
|
||||
ctl_state_ixiy_clr = 0;
|
||||
ctl_state_ixiy_we = 0;
|
||||
ctl_state_halt_set = 0;
|
||||
ctl_state_tbl_ed_set = 0;
|
||||
ctl_state_tbl_cb_set = 0;
|
||||
ctl_state_alu = 0;
|
||||
ctl_repeat_we = 0;
|
||||
ctl_state_tbl_we = 0;
|
||||
|
||||
// Module: control/interrupts.v
|
||||
ctl_iff1_iff2 = 0;
|
||||
ctl_iffx_we = 0;
|
||||
ctl_iffx_bit = 0;
|
||||
ctl_im_we = 0;
|
||||
ctl_no_ints = 0;
|
||||
|
||||
// Module: control/ir.v
|
||||
ctl_ir_we = 0;
|
||||
|
||||
// Module: control/memory_ifc.v
|
||||
ctl_mRead = 0;
|
||||
ctl_mWrite = 0;
|
||||
ctl_iorw = 0;
|
||||
|
||||
// Module: alu/alu_control.v
|
||||
ctl_shift_en = 0;
|
||||
ctl_daa_oe = 0;
|
||||
ctl_alu_op_low = 0;
|
||||
ctl_cond_short = 0;
|
||||
ctl_alu_core_hf = 0;
|
||||
ctl_eval_cond = 0;
|
||||
ctl_66_oe = 0;
|
||||
ctl_pf_sel = 0;
|
||||
|
||||
// Module: alu/alu_select.v
|
||||
ctl_alu_oe = 0;
|
||||
ctl_alu_shift_oe = 0;
|
||||
ctl_alu_op2_oe = 0;
|
||||
ctl_alu_res_oe = 0;
|
||||
ctl_alu_op1_oe = 0;
|
||||
ctl_alu_bs_oe = 0;
|
||||
ctl_alu_op1_sel_bus = 0;
|
||||
ctl_alu_op1_sel_low = 0;
|
||||
ctl_alu_op1_sel_zero = 0;
|
||||
ctl_alu_op2_sel_zero = 0;
|
||||
ctl_alu_op2_sel_bus = 0;
|
||||
ctl_alu_op2_sel_lq = 0;
|
||||
ctl_alu_sel_op2_neg = 0;
|
||||
ctl_alu_sel_op2_high = 0;
|
||||
ctl_alu_core_R = 0;
|
||||
ctl_alu_core_V = 0;
|
||||
ctl_alu_core_S = 0;
|
||||
|
||||
// Module: alu/alu_flags.v
|
||||
ctl_flags_oe = 0;
|
||||
ctl_flags_bus = 0;
|
||||
ctl_flags_alu = 0;
|
||||
ctl_flags_nf_set = 0;
|
||||
ctl_flags_cf_set = 0;
|
||||
ctl_flags_cf_cpl = 0;
|
||||
ctl_flags_cf_we = 0;
|
||||
ctl_flags_sz_we = 0;
|
||||
ctl_flags_xy_we = 0;
|
||||
ctl_flags_hf_we = 0;
|
||||
ctl_flags_pf_we = 0;
|
||||
ctl_flags_nf_we = 0;
|
||||
ctl_flags_cf2_we = 0;
|
||||
ctl_flags_hf_cpl = 0;
|
||||
ctl_flags_use_cf2 = 0;
|
||||
ctl_flags_hf2_we = 0;
|
||||
ctl_flags_nf_clr = 0;
|
||||
ctl_alu_zero_16bit = 0;
|
||||
ctl_flags_cf2_sel_shift = 0;
|
||||
ctl_flags_cf2_sel_daa = 0;
|
||||
|
||||
// Module: registers/reg_file.v
|
||||
ctl_sw_4u = 0;
|
||||
ctl_reg_in_hi = 0;
|
||||
ctl_reg_in_lo = 0;
|
||||
ctl_reg_out_lo = 0;
|
||||
ctl_reg_out_hi = 0;
|
||||
|
||||
// Module: registers/reg_control.v
|
||||
ctl_reg_exx = 0;
|
||||
ctl_reg_ex_af = 0;
|
||||
ctl_reg_ex_de_hl = 0;
|
||||
ctl_reg_use_sp = 0;
|
||||
ctl_reg_sel_pc = 0;
|
||||
ctl_reg_sel_ir = 0;
|
||||
ctl_reg_sel_wz = 0;
|
||||
ctl_reg_gp_we = 0;
|
||||
ctl_reg_not_pc = 0;
|
||||
ctl_reg_sys_we_lo = 0;
|
||||
ctl_reg_sys_we_hi = 0;
|
||||
ctl_reg_sys_we = 0;
|
||||
ctl_sw_4d = 0;
|
||||
ctl_reg_gp_hilo = 0;
|
||||
ctl_reg_gp_sel = 0;
|
||||
ctl_reg_sys_hilo = 0;
|
||||
|
||||
// Module: bus/address_latch.v
|
||||
ctl_inc_cy = 0;
|
||||
ctl_inc_dec = 0;
|
||||
ctl_al_we = 0;
|
||||
ctl_inc_limit6 = 0;
|
||||
ctl_bus_inc_oe = 0;
|
||||
ctl_apin_mux = 0;
|
||||
ctl_apin_mux2 = 0;
|
||||
|
||||
// Module: bus/bus_control.v
|
||||
ctl_bus_ff_oe = 0;
|
||||
ctl_bus_zero_oe = 0;
|
||||
|
||||
// Module: bus/bus_switch.v
|
||||
ctl_sw_1u = 0;
|
||||
ctl_sw_1d = 0;
|
||||
ctl_sw_2u = 0;
|
||||
ctl_sw_2d = 0;
|
||||
ctl_sw_mask543_en = 0;
|
||||
|
||||
// Module: bus/data_pins.v
|
||||
ctl_bus_db_we = 0;
|
||||
ctl_bus_db_oe = 0;
|
||||
171
fpga/tb/az80/execute.v
Normal file
171
fpga/tb/az80/execute.v
Normal file
@ -0,0 +1,171 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
//=============================================================================
|
||||
// This module implements the instruction execute state logic.
|
||||
//
|
||||
// Copyright (C) 2014-2016 Goran Devic
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//=============================================================================
|
||||
// Using a compiled format will include files generated by "gencompile.py" script
|
||||
// These files are a processed version of "exec_matrix_compiled.vh"
|
||||
// You would define this on Xilinx and undefine (comment out) on Altera
|
||||
`define USE_COMPILED_FORMAT
|
||||
|
||||
module execute
|
||||
(
|
||||
//----------------------------------------------------------
|
||||
// Control signals generated by the instruction execution
|
||||
//----------------------------------------------------------
|
||||
`include "exec_module.vh"
|
||||
|
||||
output reg nextM, // Last M cycle of any instruction
|
||||
output reg setM1, // Last T clock of any instruction
|
||||
output reg fFetch, // Function: opcode fetch cycle ("M1")
|
||||
output reg fMRead, // Function: memory read cycle
|
||||
output reg fMWrite, // Function: memory write cycle
|
||||
output reg fIORead, // Function: IO Read cycle
|
||||
output reg fIOWrite, // Function: IO Write cycle
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Inputs from the instruction decode PLA
|
||||
//----------------------------------------------------------
|
||||
input wire [104:0] pla, // Statically decoded instructions
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Inputs from various blocks
|
||||
//----------------------------------------------------------
|
||||
input wire in_intr, // Servicing maskable interrupt
|
||||
input wire in_nmi, // Servicing non-maskable interrupt
|
||||
input wire in_halt, // Currently in HALT mode
|
||||
input wire im1, // Interrupt Mode 1
|
||||
input wire im2, // Interrupt Mode 2
|
||||
input wire use_ixiy, // Special decode signal
|
||||
input wire flags_cond_true, // Flags condition is true
|
||||
input wire repeat_en, // Enable repeat of a block instruction
|
||||
input wire flags_zf, // ZF to test a condition
|
||||
input wire flags_nf, // NF to test for subtraction
|
||||
input wire flags_sf, // SF to test for 8-bit sign of a value
|
||||
input wire flags_cf, // CF to set HF for CCF
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Machine and clock cycles
|
||||
//----------------------------------------------------------
|
||||
input wire M1, // Machine cycle #1
|
||||
input wire M2, // Machine cycle #2
|
||||
input wire M3, // Machine cycle #3
|
||||
input wire M4, // Machine cycle #4
|
||||
input wire M5, // Machine cycle #5
|
||||
input wire T1, // T-cycle #1
|
||||
input wire T2, // T-cycle #2
|
||||
input wire T3, // T-cycle #3
|
||||
input wire T4, // T-cycle #4
|
||||
input wire T5, // T-cycle #5
|
||||
input wire T6 // T-cycle #6
|
||||
);
|
||||
|
||||
// Detects unknown instructions by signalling the known ones
|
||||
reg validPLA; // Valid PLA asserts this reg
|
||||
// Activates a state machine to compute WZ=IX+d; takes 5T cycles
|
||||
reg ixy_d; // Compute WX=IX+d
|
||||
// Signals the setting of IX/IY prefix flags; inhibits clearing them
|
||||
reg setIXIY; // Set IX/IY flag at the next T cycle
|
||||
// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)
|
||||
reg nonRep; // Non-repeating block instruction
|
||||
// Suspends incrementing PC through address latch unless in HALT or interrupt mode
|
||||
reg pc_inc_hold; // Normally 0 unless in one of those modes
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Define various shortcuts to field naming
|
||||
//--------------------------------------------------------------
|
||||
`define GP_REG_BC 2'h0
|
||||
`define GP_REG_DE 2'h1
|
||||
`define GP_REG_HL 2'h2
|
||||
`define GP_REG_AF 2'h3
|
||||
|
||||
`define PFSEL_P 2'h0
|
||||
`define PFSEL_V 2'h1
|
||||
`define PFSEL_IFF2 2'h2
|
||||
`define PFSEL_REP 2'h3
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Make available different bits and sections of the opcode byte
|
||||
//--------------------------------------------------------------
|
||||
wire op0 = pla[99];
|
||||
wire op1 = pla[100];
|
||||
wire op2 = pla[101];
|
||||
wire op3 = pla[102];
|
||||
wire op4 = pla[103];
|
||||
wire op5 = pla[104];
|
||||
|
||||
wire [1:0] op21 = { pla[101], pla[100] };
|
||||
wire [1:0] op54 = { pla[104], pla[103] };
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 8-bit register selections needs to swizzle mux for A and F
|
||||
//--------------------------------------------------------------
|
||||
wire rsel0 = op0 ^ (op1 & op2);
|
||||
wire rsel3 = op3 ^ (op4 & op5);
|
||||
|
||||
`ifdef USE_COMPILED_FORMAT
|
||||
`include "temp_wires.vh" // Define all temp wires used with compiled equations
|
||||
`endif
|
||||
|
||||
always @(*) // always_comb
|
||||
begin
|
||||
//-----------------------------------------------------------------------------
|
||||
// Default assignment of all control outputs to 0 to prevent generating latches
|
||||
//-----------------------------------------------------------------------------
|
||||
`include "exec_zero.vh" // Initial assignment to all ctl wires to zero
|
||||
|
||||
// Reset internal control regs
|
||||
validPLA = 0; // Will be set by every *valid* PLA entry
|
||||
nextM = 0; // Will be set to advance to the next M cycle
|
||||
setM1 = 0; // Will be set on a last M/T cycle of an instruction
|
||||
|
||||
// Reset global machine cycle functions
|
||||
fFetch = M1; // Fetch is aliased to M1
|
||||
fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;
|
||||
ixy_d = 0;
|
||||
setIXIY = 0;
|
||||
nonRep = 0;
|
||||
pc_inc_hold = 0;
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// State-based signal assignment; code generated from Timings spreadsheet
|
||||
//-------------------------------------------------------------------------
|
||||
`ifdef USE_COMPILED_FORMAT
|
||||
`include "exec_matrix_compiled.vh" // Compiled execution equations
|
||||
`else
|
||||
`include "exec_matrix.vh" // Execution statements in the original nested-if format
|
||||
`endif
|
||||
|
||||
// Needed by data bus 0 override logic, make only one bus writer active at any time
|
||||
ctl_bus_db_oe = ctl_bus_db_oe & ~(ctl_bus_zero_oe | ctl_bus_ff_oe);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
303
fpga/tb/az80/globals.vh
Normal file
303
fpga/tb/az80/globals.vh
Normal file
@ -0,0 +1,303 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Automatically generated by genglobals.py
|
||||
|
||||
// Module: control/clk_delay.v
|
||||
wire hold_clk_iorq;
|
||||
wire hold_clk_wait;
|
||||
wire iorq_Tw;
|
||||
wire busack;
|
||||
wire pin_control_oe;
|
||||
wire hold_clk_busrq;
|
||||
wire nhold_clk_wait;
|
||||
|
||||
// Module: control/decode_state.v
|
||||
wire in_halt;
|
||||
wire table_cb;
|
||||
wire table_ed;
|
||||
wire table_xx;
|
||||
wire use_ix;
|
||||
wire use_ixiy;
|
||||
wire in_alu;
|
||||
wire repeat_en;
|
||||
|
||||
// Module: control/exec_module.vh
|
||||
wire ctl_state_iy_set;
|
||||
wire ctl_state_ixiy_clr;
|
||||
wire ctl_state_ixiy_we;
|
||||
wire ctl_state_halt_set;
|
||||
wire ctl_state_tbl_ed_set;
|
||||
wire ctl_state_tbl_cb_set;
|
||||
wire ctl_state_alu;
|
||||
wire ctl_repeat_we;
|
||||
wire ctl_state_tbl_we;
|
||||
wire ctl_iff1_iff2;
|
||||
wire ctl_iffx_we;
|
||||
wire ctl_iffx_bit;
|
||||
wire ctl_im_we;
|
||||
wire ctl_no_ints;
|
||||
wire ctl_ir_we;
|
||||
wire ctl_mRead;
|
||||
wire ctl_mWrite;
|
||||
wire ctl_iorw;
|
||||
wire ctl_shift_en;
|
||||
wire ctl_daa_oe;
|
||||
wire ctl_alu_op_low;
|
||||
wire ctl_cond_short;
|
||||
wire ctl_alu_core_hf;
|
||||
wire ctl_eval_cond;
|
||||
wire ctl_66_oe;
|
||||
wire [1:0] ctl_pf_sel;
|
||||
wire ctl_alu_oe;
|
||||
wire ctl_alu_shift_oe;
|
||||
wire ctl_alu_op2_oe;
|
||||
wire ctl_alu_res_oe;
|
||||
wire ctl_alu_op1_oe;
|
||||
wire ctl_alu_bs_oe;
|
||||
wire ctl_alu_op1_sel_bus;
|
||||
wire ctl_alu_op1_sel_low;
|
||||
wire ctl_alu_op1_sel_zero;
|
||||
wire ctl_alu_op2_sel_zero;
|
||||
wire ctl_alu_op2_sel_bus;
|
||||
wire ctl_alu_op2_sel_lq;
|
||||
wire ctl_alu_sel_op2_neg;
|
||||
wire ctl_alu_sel_op2_high;
|
||||
wire ctl_alu_core_R;
|
||||
wire ctl_alu_core_V;
|
||||
wire ctl_alu_core_S;
|
||||
wire ctl_flags_oe;
|
||||
wire ctl_flags_bus;
|
||||
wire ctl_flags_alu;
|
||||
wire ctl_flags_nf_set;
|
||||
wire ctl_flags_cf_set;
|
||||
wire ctl_flags_cf_cpl;
|
||||
wire ctl_flags_cf_we;
|
||||
wire ctl_flags_sz_we;
|
||||
wire ctl_flags_xy_we;
|
||||
wire ctl_flags_hf_we;
|
||||
wire ctl_flags_pf_we;
|
||||
wire ctl_flags_nf_we;
|
||||
wire ctl_flags_cf2_we;
|
||||
wire ctl_flags_hf_cpl;
|
||||
wire ctl_flags_use_cf2;
|
||||
wire ctl_flags_hf2_we;
|
||||
wire ctl_flags_nf_clr;
|
||||
wire ctl_alu_zero_16bit;
|
||||
wire ctl_flags_cf2_sel_shift;
|
||||
wire ctl_flags_cf2_sel_daa;
|
||||
wire ctl_sw_4u;
|
||||
wire ctl_reg_in_hi;
|
||||
wire ctl_reg_in_lo;
|
||||
wire ctl_reg_out_lo;
|
||||
wire ctl_reg_out_hi;
|
||||
wire ctl_reg_exx;
|
||||
wire ctl_reg_ex_af;
|
||||
wire ctl_reg_ex_de_hl;
|
||||
wire ctl_reg_use_sp;
|
||||
wire ctl_reg_sel_pc;
|
||||
wire ctl_reg_sel_ir;
|
||||
wire ctl_reg_sel_wz;
|
||||
wire ctl_reg_gp_we;
|
||||
wire ctl_reg_not_pc;
|
||||
wire ctl_reg_sys_we_lo;
|
||||
wire ctl_reg_sys_we_hi;
|
||||
wire ctl_reg_sys_we;
|
||||
wire ctl_sw_4d;
|
||||
wire [1:0] ctl_reg_gp_hilo;
|
||||
wire [1:0] ctl_reg_gp_sel;
|
||||
wire [1:0] ctl_reg_sys_hilo;
|
||||
wire ctl_inc_cy;
|
||||
wire ctl_inc_dec;
|
||||
wire ctl_al_we;
|
||||
wire ctl_inc_limit6;
|
||||
wire ctl_bus_inc_oe;
|
||||
wire ctl_apin_mux;
|
||||
wire ctl_apin_mux2;
|
||||
wire ctl_bus_ff_oe;
|
||||
wire ctl_bus_zero_oe;
|
||||
wire ctl_sw_1u;
|
||||
wire ctl_sw_1d;
|
||||
wire ctl_sw_2u;
|
||||
wire ctl_sw_2d;
|
||||
wire ctl_sw_mask543_en;
|
||||
wire ctl_bus_db_we;
|
||||
wire ctl_bus_db_oe;
|
||||
|
||||
// Module: control/execute.v
|
||||
wire nextM;
|
||||
wire setM1;
|
||||
wire fFetch;
|
||||
wire fMRead;
|
||||
wire fMWrite;
|
||||
wire fIORead;
|
||||
wire fIOWrite;
|
||||
|
||||
// Module: control/interrupts.v
|
||||
wire iff2;
|
||||
wire im1;
|
||||
wire im2;
|
||||
wire in_nmi;
|
||||
wire in_intr;
|
||||
|
||||
// Module: control/ir.v
|
||||
wire [7:0] opcode;
|
||||
|
||||
// Module: control/pin_control.v
|
||||
wire bus_ab_pin_we;
|
||||
wire bus_db_pin_oe;
|
||||
wire bus_db_pin_re;
|
||||
|
||||
// Module: control/pla_decode.v
|
||||
wire [104:0] pla;
|
||||
|
||||
// Module: control/resets.v
|
||||
wire clrpc;
|
||||
wire nreset;
|
||||
|
||||
// Module: control/memory_ifc.v
|
||||
wire nM1_out;
|
||||
wire nRFSH_out;
|
||||
wire nMREQ_out;
|
||||
wire nRD_out;
|
||||
wire nWR_out;
|
||||
wire nIORQ_out;
|
||||
wire latch_wait;
|
||||
wire wait_m1;
|
||||
|
||||
// Module: control/sequencer.v
|
||||
wire M1;
|
||||
wire M2;
|
||||
wire M3;
|
||||
wire M4;
|
||||
wire M5;
|
||||
wire T1;
|
||||
wire T2;
|
||||
wire T3;
|
||||
wire T4;
|
||||
wire T5;
|
||||
wire T6;
|
||||
wire timings_en;
|
||||
|
||||
// Module: alu/alu_control.v
|
||||
wire alu_shift_in;
|
||||
wire alu_shift_right;
|
||||
wire alu_shift_left;
|
||||
wire shift_cf_out;
|
||||
wire alu_parity_in;
|
||||
wire flags_cond_true;
|
||||
wire daa_cf_out;
|
||||
wire pf_sel;
|
||||
wire alu_op_low;
|
||||
wire alu_core_cf_in;
|
||||
wire [7:0] db;
|
||||
|
||||
// Module: alu/alu_select.v
|
||||
wire alu_oe;
|
||||
wire alu_shift_oe;
|
||||
wire alu_op2_oe;
|
||||
wire alu_res_oe;
|
||||
wire alu_op1_oe;
|
||||
wire alu_bs_oe;
|
||||
wire alu_op1_sel_bus;
|
||||
wire alu_op1_sel_low;
|
||||
wire alu_op1_sel_zero;
|
||||
wire alu_op2_sel_zero;
|
||||
wire alu_op2_sel_bus;
|
||||
wire alu_op2_sel_lq;
|
||||
wire alu_sel_op2_neg;
|
||||
wire alu_sel_op2_high;
|
||||
wire alu_core_R;
|
||||
wire alu_core_V;
|
||||
wire alu_core_S;
|
||||
|
||||
// Module: alu/alu_flags.v
|
||||
wire flags_sf;
|
||||
wire flags_zf;
|
||||
wire flags_hf;
|
||||
wire flags_pf;
|
||||
wire flags_cf;
|
||||
wire flags_nf;
|
||||
wire flags_cf_latch;
|
||||
wire flags_hf2;
|
||||
|
||||
// Module: alu/alu.v
|
||||
wire alu_zero;
|
||||
wire alu_parity_out;
|
||||
wire alu_high_eq_9;
|
||||
wire alu_high_gt_9;
|
||||
wire alu_low_gt_9;
|
||||
wire alu_shift_db0;
|
||||
wire alu_shift_db7;
|
||||
wire alu_core_cf_out;
|
||||
wire alu_sf_out;
|
||||
wire alu_yf_out;
|
||||
wire alu_xf_out;
|
||||
wire alu_vf_out;
|
||||
wire [3:0] test_db_high;
|
||||
wire [3:0] test_db_low;
|
||||
|
||||
// Module: registers/reg_control.v
|
||||
wire reg_sel_bc;
|
||||
wire reg_sel_bc2;
|
||||
wire reg_sel_ix;
|
||||
wire reg_sel_iy;
|
||||
wire reg_sel_de;
|
||||
wire reg_sel_hl;
|
||||
wire reg_sel_de2;
|
||||
wire reg_sel_hl2;
|
||||
wire reg_sel_af;
|
||||
wire reg_sel_af2;
|
||||
wire reg_sel_wz;
|
||||
wire reg_sel_pc;
|
||||
wire reg_sel_ir;
|
||||
wire reg_sel_sp;
|
||||
wire reg_sel_gp_hi;
|
||||
wire reg_sel_gp_lo;
|
||||
wire reg_sel_sys_lo;
|
||||
wire reg_sel_sys_hi;
|
||||
wire reg_gp_we;
|
||||
wire reg_sys_we_lo;
|
||||
wire reg_sys_we_hi;
|
||||
wire reg_sw_4d_lo;
|
||||
wire reg_sw_4d_hi;
|
||||
|
||||
// Module: bus/address_latch.v
|
||||
wire address_is_1;
|
||||
wire [15:0] address;
|
||||
|
||||
// Module: bus/address_pins.v
|
||||
wire [15:0] abus;
|
||||
|
||||
// Module: bus/bus_switch.v
|
||||
wire bus_sw_1u;
|
||||
wire bus_sw_1d;
|
||||
wire bus_sw_2u;
|
||||
wire bus_sw_2d;
|
||||
wire bus_sw_mask543_en;
|
||||
|
||||
// Module: bus/control_pins_n.v
|
||||
wire nmi;
|
||||
wire busrq;
|
||||
wire clk;
|
||||
wire intr;
|
||||
wire mwait;
|
||||
wire reset_in;
|
||||
wire pin_nM1;
|
||||
wire pin_nMREQ;
|
||||
wire pin_nIORQ;
|
||||
wire pin_nRD;
|
||||
wire pin_nWR;
|
||||
wire pin_nRFSH;
|
||||
wire pin_nHALT;
|
||||
wire pin_nBUSACK;
|
||||
194
fpga/tb/az80/inc_dec.v
Normal file
194
fpga/tb/az80/inc_dec.v
Normal file
@ -0,0 +1,194 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:30:20 2014"
|
||||
|
||||
module inc_dec(
|
||||
carry_in,
|
||||
limit6,
|
||||
decrement,
|
||||
d,
|
||||
address
|
||||
);
|
||||
|
||||
|
||||
input wire carry_in;
|
||||
input wire limit6;
|
||||
input wire decrement;
|
||||
input wire [15:0] d;
|
||||
output wire [15:0] address;
|
||||
|
||||
wire [15:0] address_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_40;
|
||||
wire SYNTHESIZED_WIRE_41;
|
||||
wire SYNTHESIZED_WIRE_42;
|
||||
wire SYNTHESIZED_WIRE_43;
|
||||
wire SYNTHESIZED_WIRE_44;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_45;
|
||||
wire SYNTHESIZED_WIRE_46;
|
||||
wire SYNTHESIZED_WIRE_47;
|
||||
wire SYNTHESIZED_WIRE_48;
|
||||
wire SYNTHESIZED_WIRE_49;
|
||||
wire SYNTHESIZED_WIRE_50;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_51;
|
||||
wire SYNTHESIZED_WIRE_52;
|
||||
wire SYNTHESIZED_WIRE_53;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_22;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_38;
|
||||
wire SYNTHESIZED_WIRE_39;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45;
|
||||
|
||||
assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16;
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_0(
|
||||
.carry_borrow_in(carry_in),
|
||||
.d1_in(d[1]),
|
||||
.d0_in(d[0]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_40),
|
||||
.dec0_in(SYNTHESIZED_WIRE_41),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_22),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[1]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[0]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_10(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_51),
|
||||
.d1_in(d[13]),
|
||||
.d0_in(d[12]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_53),
|
||||
.dec0_in(SYNTHESIZED_WIRE_52),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_37),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[13]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[12]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_2(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_22),
|
||||
.d1_in(d[3]),
|
||||
.d0_in(d[2]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_45),
|
||||
.dec0_in(SYNTHESIZED_WIRE_42),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_25),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[3]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[2]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_4(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_25),
|
||||
.d1_in(d[5]),
|
||||
.d0_in(d[4]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_43),
|
||||
.dec0_in(SYNTHESIZED_WIRE_44),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_39),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[5]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[4]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_7(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_47),
|
||||
.d1_in(d[8]),
|
||||
.d0_in(d[7]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_46),
|
||||
.dec0_in(SYNTHESIZED_WIRE_48),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_31),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[8]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[7]));
|
||||
|
||||
|
||||
inc_dec_2bit b2v_dual_adder_9(
|
||||
.carry_borrow_in(SYNTHESIZED_WIRE_31),
|
||||
.d1_in(d[10]),
|
||||
.d0_in(d[9]),
|
||||
.dec1_in(SYNTHESIZED_WIRE_50),
|
||||
.dec0_in(SYNTHESIZED_WIRE_49),
|
||||
.carry_borrow_out(SYNTHESIZED_WIRE_36),
|
||||
.d1_out(address_ALTERA_SYNTHESIZED[10]),
|
||||
.d0_out(address_ALTERA_SYNTHESIZED[9]));
|
||||
|
||||
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = ~limit6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_41 = d[0] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_40 = d[1] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_50 = d[10] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = d[11] ^ decrement;
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11];
|
||||
|
||||
assign SYNTHESIZED_WIRE_52 = d[12] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_53 = d[13] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = d[14] ^ decrement;
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14];
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15];
|
||||
|
||||
assign SYNTHESIZED_WIRE_42 = d[2] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_45 = d[3] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_44 = d[4] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_43 = d[5] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = d[6] ^ decrement;
|
||||
|
||||
assign address_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6];
|
||||
|
||||
assign SYNTHESIZED_WIRE_48 = d[7] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_46 = d[8] ^ decrement;
|
||||
|
||||
assign SYNTHESIZED_WIRE_49 = d[9] ^ decrement;
|
||||
|
||||
assign address = address_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
67
fpga/tb/az80/inc_dec_2bit.v
Normal file
67
fpga/tb/az80/inc_dec_2bit.v
Normal file
@ -0,0 +1,67 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Mon Oct 13 12:26:57 2014"
|
||||
|
||||
module inc_dec_2bit(
|
||||
carry_borrow_in,
|
||||
d1_in,
|
||||
d0_in,
|
||||
dec1_in,
|
||||
dec0_in,
|
||||
carry_borrow_out,
|
||||
d1_out,
|
||||
d0_out
|
||||
);
|
||||
|
||||
|
||||
input wire carry_borrow_in;
|
||||
input wire d1_in;
|
||||
input wire d0_in;
|
||||
input wire dec1_in;
|
||||
input wire dec0_in;
|
||||
output wire carry_borrow_out;
|
||||
output wire d1_out;
|
||||
output wire d0_out;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in;
|
||||
|
||||
assign carry_borrow_out = dec0_in & dec1_in & carry_borrow_in;
|
||||
|
||||
assign d1_out = d1_in ^ SYNTHESIZED_WIRE_0;
|
||||
|
||||
assign d0_out = carry_borrow_in ^ d0_in;
|
||||
|
||||
|
||||
endmodule
|
||||
259
fpga/tb/az80/interrupts.v
Normal file
259
fpga/tb/az80/interrupts.v
Normal file
@ -0,0 +1,259 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Feb 13 19:23:03 2016"
|
||||
|
||||
module interrupts(
|
||||
ctl_iff1_iff2,
|
||||
nmi,
|
||||
setM1,
|
||||
intr,
|
||||
ctl_iffx_we,
|
||||
ctl_iffx_bit,
|
||||
ctl_im_we,
|
||||
clk,
|
||||
ctl_no_ints,
|
||||
nreset,
|
||||
db,
|
||||
iff2,
|
||||
im1,
|
||||
im2,
|
||||
in_nmi,
|
||||
in_intr
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_iff1_iff2;
|
||||
input wire nmi;
|
||||
input wire setM1;
|
||||
input wire intr;
|
||||
input wire ctl_iffx_we;
|
||||
input wire ctl_iffx_bit;
|
||||
input wire ctl_im_we;
|
||||
input wire clk;
|
||||
input wire ctl_no_ints;
|
||||
input wire nreset;
|
||||
input wire [1:0] db;
|
||||
output wire iff2;
|
||||
output reg im1;
|
||||
output reg im2;
|
||||
output wire in_nmi;
|
||||
output wire in_intr;
|
||||
|
||||
reg iff1;
|
||||
wire in_intr_ALTERA_SYNTHESIZED;
|
||||
reg in_nmi_ALTERA_SYNTHESIZED;
|
||||
reg int_armed;
|
||||
reg nmi_armed;
|
||||
wire test1;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
reg DFFE_instIFF2;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
reg DFFE_inst44;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
|
||||
assign iff2 = DFFE_instIFF2;
|
||||
assign SYNTHESIZED_WIRE_10 = 1;
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~ctl_iff1_iff2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = ~db[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ~in_nmi_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = db[1] & db[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4;
|
||||
|
||||
|
||||
assign in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = iff1 & intr;
|
||||
|
||||
assign test1 = setM1 & SYNTHESIZED_WIRE_8;
|
||||
|
||||
|
||||
always@(posedge nmi or negedge SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_9)
|
||||
begin
|
||||
nmi_armed <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
nmi_armed <= SYNTHESIZED_WIRE_10;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
in_nmi_ALTERA_SYNTHESIZED <= 0;
|
||||
end
|
||||
else
|
||||
if (test1)
|
||||
begin
|
||||
in_nmi_ALTERA_SYNTHESIZED <= nmi_armed;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_inst44 <= 0;
|
||||
end
|
||||
else
|
||||
if (test1)
|
||||
begin
|
||||
DFFE_inst44 <= int_armed;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_12)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_12)
|
||||
begin
|
||||
int_armed <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
int_armed <= SYNTHESIZED_WIRE_13;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = ~ctl_no_ints;
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_15)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_15)
|
||||
begin
|
||||
iff1 <= 0;
|
||||
end
|
||||
else
|
||||
if (SYNTHESIZED_WIRE_17)
|
||||
begin
|
||||
iff1 <= SYNTHESIZED_WIRE_16;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_21)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_21)
|
||||
begin
|
||||
DFFE_instIFF2 <= 0;
|
||||
end
|
||||
else
|
||||
if (ctl_iffx_we)
|
||||
begin
|
||||
DFFE_instIFF2 <= ctl_iffx_bit;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
im1 <= 0;
|
||||
end
|
||||
else
|
||||
if (ctl_im_we)
|
||||
begin
|
||||
im1 <= SYNTHESIZED_WIRE_19;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
im2 <= 0;
|
||||
end
|
||||
else
|
||||
if (ctl_im_we)
|
||||
begin
|
||||
im2 <= SYNTHESIZED_WIRE_20;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = ~in_intr_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = ~in_intr_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = ~in_nmi_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign in_nmi = in_nmi_ALTERA_SYNTHESIZED;
|
||||
assign in_intr = in_intr_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
71
fpga/tb/az80/ir.v
Normal file
71
fpga/tb/az80/ir.v
Normal file
@ -0,0 +1,71 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 08:56:46 2016"
|
||||
|
||||
module ir(
|
||||
ctl_ir_we,
|
||||
clk,
|
||||
nreset,
|
||||
nhold_clk_wait,
|
||||
db,
|
||||
opcode
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_ir_we;
|
||||
input wire clk;
|
||||
input wire nreset;
|
||||
input wire nhold_clk_wait;
|
||||
input wire [7:0] db;
|
||||
output reg [7:0] opcode;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
opcode[7:0] <= 8'b00000000;
|
||||
end
|
||||
else
|
||||
if (SYNTHESIZED_WIRE_0)
|
||||
begin
|
||||
opcode[7:0] <= db[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
443
fpga/tb/az80/memory_ifc.v
Normal file
443
fpga/tb/az80/memory_ifc.v
Normal file
@ -0,0 +1,443 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sun Dec 09 19:14:29 2018"
|
||||
|
||||
module memory_ifc(
|
||||
clk,
|
||||
nM1_int,
|
||||
ctl_mRead,
|
||||
ctl_mWrite,
|
||||
in_intr,
|
||||
nreset,
|
||||
fIORead,
|
||||
fIOWrite,
|
||||
setM1,
|
||||
ctl_iorw,
|
||||
timings_en,
|
||||
iorq_Tw,
|
||||
nhold_clk_wait,
|
||||
nM1_out,
|
||||
nRFSH_out,
|
||||
nMREQ_out,
|
||||
nRD_out,
|
||||
nWR_out,
|
||||
nIORQ_out,
|
||||
latch_wait,
|
||||
wait_m1
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire nM1_int;
|
||||
input wire ctl_mRead;
|
||||
input wire ctl_mWrite;
|
||||
input wire in_intr;
|
||||
input wire nreset;
|
||||
input wire fIORead;
|
||||
input wire fIOWrite;
|
||||
input wire setM1;
|
||||
input wire ctl_iorw;
|
||||
input wire timings_en;
|
||||
input wire iorq_Tw;
|
||||
input wire nhold_clk_wait;
|
||||
output wire nM1_out;
|
||||
output wire nRFSH_out;
|
||||
output wire nMREQ_out;
|
||||
output wire nRD_out;
|
||||
output wire nWR_out;
|
||||
output wire nIORQ_out;
|
||||
output wire latch_wait;
|
||||
output wire wait_m1;
|
||||
|
||||
wire intr_iorq;
|
||||
wire ioRead;
|
||||
wire iorq;
|
||||
wire ioWrite;
|
||||
wire m1_mreq;
|
||||
wire mrd_mreq;
|
||||
wire mwr_mreq;
|
||||
reg mwr_wr;
|
||||
wire nMEMRQ_int;
|
||||
wire nq2;
|
||||
reg q1;
|
||||
reg q2;
|
||||
wire wait_io;
|
||||
reg wait_iorq;
|
||||
reg wait_iorqinta;
|
||||
reg wait_m_ALTERA_SYNTHESIZED1;
|
||||
reg wait_mrd;
|
||||
reg wait_mwr;
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
reg DFFE_m1_ff3;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
reg DFFE_iorq_ff4;
|
||||
reg SYNTHESIZED_WIRE_15;
|
||||
reg DFFE_mrd_ff3;
|
||||
reg DFFE_intr_ff3;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
reg SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
reg SYNTHESIZED_WIRE_17;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
reg DFFE_iorq_ff1;
|
||||
reg DFFE_m1_ff1;
|
||||
reg DFFE_mrd_ff1;
|
||||
reg DFFE_mwr_ff1;
|
||||
reg DFFE_mreq_ff2;
|
||||
|
||||
|
||||
|
||||
|
||||
assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
|
||||
|
||||
assign ioRead = iorq & fIORead;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
|
||||
|
||||
assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
|
||||
|
||||
assign iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;
|
||||
|
||||
assign ioWrite = iorq & fIOWrite;
|
||||
|
||||
assign latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
|
||||
|
||||
assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
|
||||
|
||||
assign nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
|
||||
|
||||
assign mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
|
||||
|
||||
assign nWR_out = ~(ioWrite | mwr_wr);
|
||||
|
||||
assign mwr_mreq = mwr_wr | wait_mwr;
|
||||
|
||||
assign nIORQ_out = ~(intr_iorq | iorq);
|
||||
|
||||
assign wait_io = wait_iorqinta | wait_iorq;
|
||||
|
||||
assign intr_iorq = DFFE_intr_ff3 | wait_iorqinta;
|
||||
|
||||
assign nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);
|
||||
|
||||
assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
wait_iorqinta <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wait_iorqinta <= iorq_Tw;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_intr_ff3 <= 0;
|
||||
end
|
||||
else
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
DFFE_intr_ff3 <= wait_iorqinta;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_iorq_ff1 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_iorq_ff1 <= ctl_iorw;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_15 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
wait_iorq <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
wait_iorq <= SYNTHESIZED_WIRE_15;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_iorq_ff4 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_iorq_ff4 <= wait_iorq;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_16 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_16 <= nM1_int;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_m1_ff1 <= 1;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_m1_ff1 <= setM1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
wait_m_ALTERA_SYNTHESIZED1 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_m1_ff3 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_mrd_ff1 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_mrd_ff1 <= ctl_mRead;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
wait_mrd <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
wait_mrd <= DFFE_mrd_ff1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_mrd_ff3 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_mrd_ff3 <= wait_mrd;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_17 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_mreq_ff2 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_mwr_ff1 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
DFFE_mwr_ff1 <= ctl_mWrite;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
wait_mwr <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
wait_mwr <= DFFE_mwr_ff1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
mwr_wr <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
mwr_wr <= wait_mwr;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = ~clk;
|
||||
|
||||
assign nq2 = ~q2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ~nreset;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
q1 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
q1 <= SYNTHESIZED_WIRE_16;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
q2 <= 0;
|
||||
end
|
||||
else
|
||||
if (timings_en)
|
||||
begin
|
||||
q2 <= q1;
|
||||
end
|
||||
end
|
||||
|
||||
assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
|
||||
|
||||
endmodule
|
||||
102
fpga/tb/az80/pin_control.v
Normal file
102
fpga/tb/az80/pin_control.v
Normal file
@ -0,0 +1,102 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sun Nov 16 21:18:37 2014"
|
||||
|
||||
module pin_control(
|
||||
fFetch,
|
||||
fMRead,
|
||||
fMWrite,
|
||||
fIORead,
|
||||
fIOWrite,
|
||||
T1,
|
||||
T2,
|
||||
T3,
|
||||
T4,
|
||||
bus_ab_pin_we,
|
||||
bus_db_pin_oe,
|
||||
bus_db_pin_re
|
||||
);
|
||||
|
||||
|
||||
input wire fFetch;
|
||||
input wire fMRead;
|
||||
input wire fMWrite;
|
||||
input wire fIORead;
|
||||
input wire fIOWrite;
|
||||
input wire T1;
|
||||
input wire T2;
|
||||
input wire T3;
|
||||
input wire T4;
|
||||
output wire bus_ab_pin_we;
|
||||
output wire bus_db_pin_oe;
|
||||
output wire bus_db_pin_re;
|
||||
|
||||
wire SYNTHESIZED_WIRE_0;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
wire SYNTHESIZED_WIRE_4;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_7;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite;
|
||||
|
||||
assign SYNTHESIZED_WIRE_7 = T3 | T2;
|
||||
|
||||
assign bus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = T3 & fIORead;
|
||||
|
||||
assign bus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
|
||||
|
||||
assign bus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = T2 | T3 | T4;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7;
|
||||
|
||||
assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite;
|
||||
|
||||
assign SYNTHESIZED_WIRE_4 = T2 & fFetch;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = T2 & fMRead;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = T3 & fFetch;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9;
|
||||
|
||||
|
||||
endmodule
|
||||
134
fpga/tb/az80/pla_decode.v
Normal file
134
fpga/tb/az80/pla_decode.v
Normal file
@ -0,0 +1,134 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
//=====================================================================================
|
||||
// This file is automatically generated by the z80_pla_checker tool. Do not edit!
|
||||
//=====================================================================================
|
||||
module pla_decode
|
||||
(
|
||||
input wire [6:0] prefix,
|
||||
input wire [7:0] opcode,
|
||||
output wire [104:0] pla
|
||||
);
|
||||
|
||||
assign pla[ 0] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110100) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldx/cpx/inx/outx brk
|
||||
assign pla[ 1] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11011001) ? 1'b1 : 1'b0; // exx
|
||||
assign pla[ 2] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101011) ? 1'b1 : 1'b0; // ex de,hl
|
||||
assign pla[ 3] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11011111) == 15'b0000100_11011101) ? 1'b1 : 1'b0; // IX/IY prefix
|
||||
assign pla[ 5] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11111001) ? 1'b1 : 1'b0; // ld sp,hl
|
||||
assign pla[ 6] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101001) ? 1'b1 : 1'b0; // jp hl
|
||||
assign pla[ 7] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000001) ? 1'b1 : 1'b0; // ld rr,nn
|
||||
assign pla[ 8] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld (rr),a/a,(rr)
|
||||
assign pla[ 9] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000011) ? 1'b1 : 1'b0; // inc/dec rr
|
||||
assign pla[ 10] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11100011) ? 1'b1 : 1'b0; // ex (sp),hl
|
||||
assign pla[ 11] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100001) ? 1'b1 : 1'b0; // cpi/cpir/cpd/cpdr
|
||||
assign pla[ 12] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldi/ldir/ldd/lddr
|
||||
assign pla[ 13] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld direction
|
||||
assign pla[ 15] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01100111) ? 1'b1 : 1'b0; // rrd/rld
|
||||
assign pla[ 16] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_11000101) ? 1'b1 : 1'b0; // push rr
|
||||
assign pla[ 17] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000110) ? 1'b1 : 1'b0; // ld r,n
|
||||
assign pla[ 20] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100011) ? 1'b1 : 1'b0; // outx/otxr
|
||||
assign pla[ 21] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/inxr
|
||||
assign pla[ 23] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001011) == 15'b0000100_11000001) ? 1'b1 : 1'b0; // push/pop
|
||||
assign pla[ 24] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001101) ? 1'b1 : 1'b0; // call nn
|
||||
assign pla[ 25] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000111) ? 1'b1 : 1'b0; // rlca/rla/rrca/rra
|
||||
assign pla[ 26] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00010000) ? 1'b1 : 1'b0; // djnz e
|
||||
assign pla[ 27] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000110) == 15'b0000001_01000000) ? 1'b1 : 1'b0; // in/out r,(c)
|
||||
assign pla[ 28] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a
|
||||
assign pla[ 29] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11000011) ? 1'b1 : 1'b0; // jp nn
|
||||
assign pla[ 30] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00100010) ? 1'b1 : 1'b0; // ld hl,(nn)/(nn),hl
|
||||
assign pla[ 31] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld rr,(nn)/(nn),rr
|
||||
assign pla[ 33] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11001111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld direction
|
||||
assign pla[ 34] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000001) ? 1'b1 : 1'b0; // out (c),r
|
||||
assign pla[ 35] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001001) ? 1'b1 : 1'b0; // ret
|
||||
assign pla[ 37] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a/a,(n)
|
||||
assign pla[ 38] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00110010) ? 1'b1 : 1'b0; // ld (nn),a/a,(nn)
|
||||
assign pla[ 39] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00001000) ? 1'b1 : 1'b0; // ex af,af'
|
||||
assign pla[ 40] = (({prefix[6:0], opcode[7:0]} & 15'b0100100_11111111) == 15'b0100100_00110110) ? 1'b1 : 1'b0; // ld (ix+d),n
|
||||
assign pla[ 42] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000100) ? 1'b1 : 1'b0; // call cc,nn
|
||||
assign pla[ 43] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000010) ? 1'b1 : 1'b0; // jp cc,nn
|
||||
assign pla[ 44] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001011) ? 1'b1 : 1'b0; // CB prefix
|
||||
assign pla[ 45] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000000) ? 1'b1 : 1'b0; // ret cc
|
||||
assign pla[ 46] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000101) ? 1'b1 : 1'b0; // reti/retn
|
||||
assign pla[ 47] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00011000) ? 1'b1 : 1'b0; // jr e
|
||||
assign pla[ 48] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00100000) ? 1'b1 : 1'b0; // jr ss,e
|
||||
assign pla[ 49] = (({prefix[6:0], opcode[7:0]} & 15'b0100000_11111111) == 15'b0100000_11001011) ? 1'b1 : 1'b0; // CB prefix with IX/IY
|
||||
assign pla[ 50] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110110) ? 1'b1 : 1'b0; // ld (hl),n
|
||||
assign pla[ 51] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101101) ? 1'b1 : 1'b0; // ED prefix
|
||||
assign pla[ 52] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_10000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cp (hl)
|
||||
assign pla[ 53] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111110) == 15'b0000100_00110100) ? 1'b1 : 1'b0; // inc/dec (hl)
|
||||
assign pla[ 55] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_00000111) == 15'b0000010_00000110) ? 1'b1 : 1'b0; // Every CB op (hl)
|
||||
assign pla[ 56] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000111) ? 1'b1 : 1'b0; // rst p
|
||||
assign pla[ 57] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01000111) ? 1'b1 : 1'b0; // ld i,a/r,a
|
||||
assign pla[ 58] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11000111) == 15'b0010100_01000110) ? 1'b1 : 1'b0; // ld r,(hl)
|
||||
assign pla[ 59] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11111000) == 15'b0010100_01110000) ? 1'b1 : 1'b0; // ld (hl),r
|
||||
assign pla[ 61] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_01000000) ? 1'b1 : 1'b0; // ld r,r'
|
||||
assign pla[ 64] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,imm
|
||||
assign pla[ 65] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_10000000) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,r
|
||||
assign pla[ 66] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000110) == 15'b0000100_00000100) ? 1'b1 : 1'b0; // inc/dec r
|
||||
assign pla[ 68] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000010) ? 1'b1 : 1'b0; // adc/sbc hl,rr
|
||||
assign pla[ 69] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00001001) ? 1'b1 : 1'b0; // add hl,rr
|
||||
assign pla[ 70] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_00000000) ? 1'b1 : 1'b0; // rlc r
|
||||
assign pla[ 72] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_01000000) ? 1'b1 : 1'b0; // bit b,r
|
||||
assign pla[ 73] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_10000000) ? 1'b1 : 1'b0; // res b,r
|
||||
assign pla[ 74] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_11000000) ? 1'b1 : 1'b0; // set b,r
|
||||
assign pla[ 75] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000101) ? 1'b1 : 1'b0; // dec r
|
||||
assign pla[ 76] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00111000) ? 1'b1 : 1'b0; // 111 (CP)
|
||||
assign pla[ 77] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00100111) ? 1'b1 : 1'b0; // daa
|
||||
assign pla[ 78] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00010000) ? 1'b1 : 1'b0; // 010 (SUB)
|
||||
assign pla[ 79] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00011000) ? 1'b1 : 1'b0; // 011 (SBC)
|
||||
assign pla[ 80] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00001000) ? 1'b1 : 1'b0; // 001 (ADC)
|
||||
assign pla[ 81] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00101111) ? 1'b1 : 1'b0; // cpl
|
||||
assign pla[ 82] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000100) ? 1'b1 : 1'b0; // neg
|
||||
assign pla[ 83] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01010111) ? 1'b1 : 1'b0; // ld a,i/a,r
|
||||
assign pla[ 84] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00000000) ? 1'b1 : 1'b0; // 000 (ADD)
|
||||
assign pla[ 85] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00100000) ? 1'b1 : 1'b0; // 100 (AND)
|
||||
assign pla[ 86] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00110000) ? 1'b1 : 1'b0; // 110 (OR)
|
||||
assign pla[ 88] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00101000) ? 1'b1 : 1'b0; // 101 (XOR)
|
||||
assign pla[ 89] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00111111) ? 1'b1 : 1'b0; // ccf
|
||||
assign pla[ 91] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100110) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/outx/inxr/otxr
|
||||
assign pla[ 92] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110111) ? 1'b1 : 1'b0; // scf
|
||||
assign pla[ 95] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_01110110) ? 1'b1 : 1'b0; // halt
|
||||
assign pla[ 96] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000110) ? 1'b1 : 1'b0; // im n
|
||||
assign pla[ 97] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11110011) ? 1'b1 : 1'b0; // di/ei
|
||||
assign pla[ 99] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000001) == 15'b0000000_00000001) ? 1'b1 : 1'b0; // opcode[0]
|
||||
assign pla[100] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000010) == 15'b0000000_00000010) ? 1'b1 : 1'b0; // opcode[1]
|
||||
assign pla[101] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000100) == 15'b0000000_00000100) ? 1'b1 : 1'b0; // opcode[2]
|
||||
assign pla[102] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00001000) == 15'b0000000_00001000) ? 1'b1 : 1'b0; // opcode[3]
|
||||
assign pla[103] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00010000) == 15'b0000000_00010000) ? 1'b1 : 1'b0; // opcode[4]
|
||||
assign pla[104] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00100000) == 15'b0000000_00100000) ? 1'b1 : 1'b0; // opcode[5]
|
||||
|
||||
// Entries not used by our timing matrix
|
||||
assign pla[ 67] = 1'b0; // in
|
||||
assign pla[ 62] = 1'b0; // For all CB opcodes
|
||||
assign pla[ 54] = 1'b0; // Every CB with IX/IY
|
||||
assign pla[ 22] = 1'b0; // CB prefix w/o IX/IY
|
||||
assign pla[ 14] = 1'b0; // dec rr
|
||||
assign pla[ 4] = 1'b0; // ld x,a/a,x
|
||||
|
||||
// Duplicate entries
|
||||
assign pla[ 18] = 1'b0; // ldi/ldir/ldd/lddr
|
||||
assign pla[ 19] = 1'b0; // cpi/cpir/cpd/cpdr
|
||||
assign pla[ 32] = 1'b0; // ld i,a/a,i/r,a/a,r
|
||||
assign pla[ 36] = 1'b0; // ld(rr),a/a,(rr)
|
||||
assign pla[ 41] = 1'b0; // IX/IY
|
||||
assign pla[ 60] = 1'b0; // rrd/rld
|
||||
assign pla[ 63] = 1'b0; // ld r,*
|
||||
assign pla[ 71] = 1'b0; // rlca/rla/rrca/rra
|
||||
assign pla[ 87] = 1'b0; // ld a,i / ld a,r
|
||||
assign pla[ 90] = 1'b0; // djnz *
|
||||
assign pla[ 93] = 1'b0; // cpi/cpir/cpd/cpdr
|
||||
assign pla[ 94] = 1'b0; // ldi/ldir/ldd/lddr
|
||||
assign pla[ 98] = 1'b0; // out (*),a/in a,(*)
|
||||
|
||||
endmodule
|
||||
338
fpga/tb/az80/reg_control.v
Normal file
338
fpga/tb/az80/reg_control.v
Normal file
@ -0,0 +1,338 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 09:05:10 2016"
|
||||
|
||||
module reg_control(
|
||||
ctl_reg_exx,
|
||||
ctl_reg_ex_af,
|
||||
ctl_reg_ex_de_hl,
|
||||
ctl_reg_use_sp,
|
||||
nreset,
|
||||
ctl_reg_sel_pc,
|
||||
ctl_reg_sel_ir,
|
||||
ctl_reg_sel_wz,
|
||||
ctl_reg_gp_we,
|
||||
ctl_reg_not_pc,
|
||||
use_ixiy,
|
||||
use_ix,
|
||||
ctl_reg_sys_we_lo,
|
||||
ctl_reg_sys_we_hi,
|
||||
ctl_reg_sys_we,
|
||||
clk,
|
||||
ctl_sw_4d,
|
||||
nhold_clk_wait,
|
||||
ctl_reg_gp_hilo,
|
||||
ctl_reg_gp_sel,
|
||||
ctl_reg_sys_hilo,
|
||||
reg_sel_bc,
|
||||
reg_sel_bc2,
|
||||
reg_sel_ix,
|
||||
reg_sel_iy,
|
||||
reg_sel_de,
|
||||
reg_sel_hl,
|
||||
reg_sel_de2,
|
||||
reg_sel_hl2,
|
||||
reg_sel_af,
|
||||
reg_sel_af2,
|
||||
reg_sel_wz,
|
||||
reg_sel_pc,
|
||||
reg_sel_ir,
|
||||
reg_sel_sp,
|
||||
reg_sel_gp_hi,
|
||||
reg_sel_gp_lo,
|
||||
reg_sel_sys_lo,
|
||||
reg_sel_sys_hi,
|
||||
reg_gp_we,
|
||||
reg_sys_we_lo,
|
||||
reg_sys_we_hi,
|
||||
reg_sw_4d_lo,
|
||||
reg_sw_4d_hi
|
||||
);
|
||||
|
||||
|
||||
input wire ctl_reg_exx;
|
||||
input wire ctl_reg_ex_af;
|
||||
input wire ctl_reg_ex_de_hl;
|
||||
input wire ctl_reg_use_sp;
|
||||
input wire nreset;
|
||||
input wire ctl_reg_sel_pc;
|
||||
input wire ctl_reg_sel_ir;
|
||||
input wire ctl_reg_sel_wz;
|
||||
input wire ctl_reg_gp_we;
|
||||
input wire ctl_reg_not_pc;
|
||||
input wire use_ixiy;
|
||||
input wire use_ix;
|
||||
input wire ctl_reg_sys_we_lo;
|
||||
input wire ctl_reg_sys_we_hi;
|
||||
input wire ctl_reg_sys_we;
|
||||
input wire clk;
|
||||
input wire ctl_sw_4d;
|
||||
input wire nhold_clk_wait;
|
||||
input wire [1:0] ctl_reg_gp_hilo;
|
||||
input wire [1:0] ctl_reg_gp_sel;
|
||||
input wire [1:0] ctl_reg_sys_hilo;
|
||||
output wire reg_sel_bc;
|
||||
output wire reg_sel_bc2;
|
||||
output wire reg_sel_ix;
|
||||
output wire reg_sel_iy;
|
||||
output wire reg_sel_de;
|
||||
output wire reg_sel_hl;
|
||||
output wire reg_sel_de2;
|
||||
output wire reg_sel_hl2;
|
||||
output wire reg_sel_af;
|
||||
output wire reg_sel_af2;
|
||||
output wire reg_sel_wz;
|
||||
output wire reg_sel_pc;
|
||||
output wire reg_sel_ir;
|
||||
output wire reg_sel_sp;
|
||||
output wire reg_sel_gp_hi;
|
||||
output wire reg_sel_gp_lo;
|
||||
output wire reg_sel_sys_lo;
|
||||
output wire reg_sel_sys_hi;
|
||||
output wire reg_gp_we;
|
||||
output wire reg_sys_we_lo;
|
||||
output wire reg_sys_we_hi;
|
||||
output wire reg_sw_4d_lo;
|
||||
output wire reg_sw_4d_hi;
|
||||
|
||||
reg bank_af;
|
||||
reg bank_exx;
|
||||
reg bank_hl_de1;
|
||||
reg bank_hl_de2;
|
||||
wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
|
||||
wire SYNTHESIZED_WIRE_52;
|
||||
wire SYNTHESIZED_WIRE_53;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_54;
|
||||
wire SYNTHESIZED_WIRE_55;
|
||||
wire SYNTHESIZED_WIRE_5;
|
||||
wire SYNTHESIZED_WIRE_56;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_57;
|
||||
wire SYNTHESIZED_WIRE_58;
|
||||
wire SYNTHESIZED_WIRE_59;
|
||||
wire SYNTHESIZED_WIRE_60;
|
||||
wire SYNTHESIZED_WIRE_21;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
wire SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_25;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire SYNTHESIZED_WIRE_61;
|
||||
wire SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_38;
|
||||
wire SYNTHESIZED_WIRE_39;
|
||||
wire SYNTHESIZED_WIRE_40;
|
||||
wire SYNTHESIZED_WIRE_41;
|
||||
wire SYNTHESIZED_WIRE_42;
|
||||
wire SYNTHESIZED_WIRE_43;
|
||||
wire SYNTHESIZED_WIRE_44;
|
||||
wire SYNTHESIZED_WIRE_45;
|
||||
wire SYNTHESIZED_WIRE_46;
|
||||
wire SYNTHESIZED_WIRE_47;
|
||||
wire SYNTHESIZED_WIRE_48;
|
||||
wire SYNTHESIZED_WIRE_49;
|
||||
wire SYNTHESIZED_WIRE_50;
|
||||
|
||||
assign reg_sel_wz = ctl_reg_sel_wz;
|
||||
assign reg_sel_ir = ctl_reg_sel_ir;
|
||||
assign reg_sel_gp_hi = ctl_reg_gp_hilo[1];
|
||||
assign reg_sel_gp_lo = ctl_reg_gp_hilo[0];
|
||||
assign reg_sel_sys_lo = ctl_reg_sys_hilo[0];
|
||||
assign reg_sel_sys_hi = ctl_reg_sys_hilo[1];
|
||||
assign reg_gp_we = ctl_reg_gp_we;
|
||||
assign reg_sw_4d_lo = ctl_sw_4d;
|
||||
|
||||
|
||||
|
||||
assign reg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53;
|
||||
|
||||
assign reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54;
|
||||
|
||||
assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5;
|
||||
|
||||
assign reg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp;
|
||||
|
||||
assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp;
|
||||
|
||||
assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
|
||||
|
||||
assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
|
||||
|
||||
assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ~bank_af;
|
||||
|
||||
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
|
||||
|
||||
assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
|
||||
|
||||
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
|
||||
|
||||
assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
|
||||
|
||||
assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
|
||||
|
||||
assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
|
||||
|
||||
assign reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;
|
||||
|
||||
assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;
|
||||
|
||||
assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
|
||||
|
||||
assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
|
||||
|
||||
assign SYNTHESIZED_WIRE_53 = ~bank_exx;
|
||||
|
||||
assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
|
||||
|
||||
assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
|
||||
|
||||
assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
|
||||
|
||||
assign SYNTHESIZED_WIRE_60 = ~bank_hl_de1;
|
||||
|
||||
assign reg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi;
|
||||
|
||||
assign reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34;
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = ~ctl_reg_not_pc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = ~ctl_reg_gp_sel[1];
|
||||
|
||||
assign reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;
|
||||
|
||||
assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
|
||||
|
||||
assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;
|
||||
|
||||
assign SYNTHESIZED_WIRE_34 = ~use_ixiy;
|
||||
|
||||
assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
bank_af <= 0;
|
||||
end
|
||||
else
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
bank_af <= bank_af ^ ctl_reg_ex_af;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = ~use_ix;
|
||||
|
||||
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
|
||||
|
||||
assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37;
|
||||
|
||||
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;
|
||||
|
||||
assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;
|
||||
|
||||
assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;
|
||||
|
||||
assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
bank_hl_de2 <= 0;
|
||||
end
|
||||
else
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;
|
||||
|
||||
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;
|
||||
|
||||
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
bank_hl_de1 <= 0;
|
||||
end
|
||||
else
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
bank_exx <= 0;
|
||||
end
|
||||
else
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
bank_exx <= bank_exx ^ ctl_reg_exx;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
|
||||
|
||||
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
|
||||
|
||||
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
|
||||
|
||||
assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
|
||||
|
||||
endmodule
|
||||
583
fpga/tb/az80/reg_file.v
Normal file
583
fpga/tb/az80/reg_file.v
Normal file
@ -0,0 +1,583 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Tue Mar 08 06:12:46 2016"
|
||||
|
||||
module reg_file(
|
||||
reg_sel_sys_lo,
|
||||
reg_sel_gp_lo,
|
||||
reg_sel_sys_hi,
|
||||
reg_sel_gp_hi,
|
||||
reg_sel_ir,
|
||||
reg_sel_pc,
|
||||
ctl_sw_4u,
|
||||
reg_sel_wz,
|
||||
reg_sel_sp,
|
||||
reg_sel_iy,
|
||||
reg_sel_ix,
|
||||
reg_sel_hl2,
|
||||
reg_sel_hl,
|
||||
reg_sel_de2,
|
||||
reg_sel_de,
|
||||
reg_sel_bc2,
|
||||
reg_sel_bc,
|
||||
reg_sel_af2,
|
||||
reg_sel_af,
|
||||
reg_gp_we,
|
||||
reg_sys_we_lo,
|
||||
reg_sys_we_hi,
|
||||
ctl_reg_in_hi,
|
||||
ctl_reg_in_lo,
|
||||
ctl_reg_out_lo,
|
||||
ctl_reg_out_hi,
|
||||
clk,
|
||||
reg_sw_4d_lo,
|
||||
reg_sw_4d_hi,
|
||||
db_hi_as,
|
||||
db_hi_ds,
|
||||
db_lo_as,
|
||||
db_lo_ds
|
||||
);
|
||||
|
||||
|
||||
input wire reg_sel_sys_lo;
|
||||
input wire reg_sel_gp_lo;
|
||||
input wire reg_sel_sys_hi;
|
||||
input wire reg_sel_gp_hi;
|
||||
input wire reg_sel_ir;
|
||||
input wire reg_sel_pc;
|
||||
input wire ctl_sw_4u;
|
||||
input wire reg_sel_wz;
|
||||
input wire reg_sel_sp;
|
||||
input wire reg_sel_iy;
|
||||
input wire reg_sel_ix;
|
||||
input wire reg_sel_hl2;
|
||||
input wire reg_sel_hl;
|
||||
input wire reg_sel_de2;
|
||||
input wire reg_sel_de;
|
||||
input wire reg_sel_bc2;
|
||||
input wire reg_sel_bc;
|
||||
input wire reg_sel_af2;
|
||||
input wire reg_sel_af;
|
||||
input wire reg_gp_we;
|
||||
input wire reg_sys_we_lo;
|
||||
input wire reg_sys_we_hi;
|
||||
input wire ctl_reg_in_hi;
|
||||
input wire ctl_reg_in_lo;
|
||||
input wire ctl_reg_out_lo;
|
||||
input wire ctl_reg_out_hi;
|
||||
input wire clk;
|
||||
input wire reg_sw_4d_lo;
|
||||
input wire reg_sw_4d_hi;
|
||||
inout wire [7:0] db_hi_as;
|
||||
inout wire [7:0] db_hi_ds;
|
||||
inout wire [7:0] db_lo_as;
|
||||
inout wire [7:0] db_lo_ds;
|
||||
|
||||
wire [7:0] gdfx_temp0;
|
||||
wire [7:0] gdfx_temp1;
|
||||
wire SYNTHESIZED_WIRE_84;
|
||||
wire SYNTHESIZED_WIRE_85;
|
||||
wire SYNTHESIZED_WIRE_86;
|
||||
wire SYNTHESIZED_WIRE_28;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_30;
|
||||
wire SYNTHESIZED_WIRE_31;
|
||||
wire SYNTHESIZED_WIRE_32;
|
||||
wire SYNTHESIZED_WIRE_33;
|
||||
wire SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_38;
|
||||
wire SYNTHESIZED_WIRE_39;
|
||||
wire SYNTHESIZED_WIRE_40;
|
||||
wire SYNTHESIZED_WIRE_41;
|
||||
wire SYNTHESIZED_WIRE_42;
|
||||
wire SYNTHESIZED_WIRE_43;
|
||||
wire SYNTHESIZED_WIRE_44;
|
||||
wire SYNTHESIZED_WIRE_45;
|
||||
wire SYNTHESIZED_WIRE_46;
|
||||
wire SYNTHESIZED_WIRE_47;
|
||||
wire SYNTHESIZED_WIRE_48;
|
||||
wire SYNTHESIZED_WIRE_49;
|
||||
wire SYNTHESIZED_WIRE_50;
|
||||
wire SYNTHESIZED_WIRE_51;
|
||||
wire SYNTHESIZED_WIRE_52;
|
||||
wire SYNTHESIZED_WIRE_53;
|
||||
wire SYNTHESIZED_WIRE_54;
|
||||
wire SYNTHESIZED_WIRE_55;
|
||||
wire SYNTHESIZED_WIRE_56;
|
||||
wire SYNTHESIZED_WIRE_57;
|
||||
wire SYNTHESIZED_WIRE_58;
|
||||
wire SYNTHESIZED_WIRE_59;
|
||||
wire SYNTHESIZED_WIRE_60;
|
||||
wire SYNTHESIZED_WIRE_61;
|
||||
wire SYNTHESIZED_WIRE_62;
|
||||
wire SYNTHESIZED_WIRE_63;
|
||||
wire SYNTHESIZED_WIRE_64;
|
||||
wire SYNTHESIZED_WIRE_65;
|
||||
wire SYNTHESIZED_WIRE_66;
|
||||
wire SYNTHESIZED_WIRE_67;
|
||||
wire SYNTHESIZED_WIRE_68;
|
||||
wire SYNTHESIZED_WIRE_69;
|
||||
wire SYNTHESIZED_WIRE_70;
|
||||
wire SYNTHESIZED_WIRE_71;
|
||||
wire SYNTHESIZED_WIRE_72;
|
||||
wire SYNTHESIZED_WIRE_73;
|
||||
wire SYNTHESIZED_WIRE_74;
|
||||
wire SYNTHESIZED_WIRE_75;
|
||||
wire SYNTHESIZED_WIRE_76;
|
||||
wire SYNTHESIZED_WIRE_77;
|
||||
wire SYNTHESIZED_WIRE_78;
|
||||
wire SYNTHESIZED_WIRE_79;
|
||||
wire SYNTHESIZED_WIRE_80;
|
||||
wire SYNTHESIZED_WIRE_81;
|
||||
wire SYNTHESIZED_WIRE_82;
|
||||
wire SYNTHESIZED_WIRE_83;
|
||||
|
||||
|
||||
|
||||
|
||||
assign SYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
|
||||
|
||||
assign SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp;
|
||||
|
||||
assign SYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_84 = ~reg_sys_we_lo;
|
||||
|
||||
assign SYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy;
|
||||
|
||||
assign SYNTHESIZED_WIRE_85 = ~reg_sys_we_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix;
|
||||
|
||||
assign SYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
|
||||
|
||||
assign SYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl;
|
||||
|
||||
assign SYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de;
|
||||
|
||||
assign SYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_86 = ~reg_gp_we;
|
||||
|
||||
assign SYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy;
|
||||
|
||||
assign SYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix;
|
||||
|
||||
assign SYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af;
|
||||
|
||||
assign SYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir;
|
||||
|
||||
assign SYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl;
|
||||
|
||||
assign SYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi;
|
||||
|
||||
assign SYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz;
|
||||
|
||||
assign SYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de;
|
||||
|
||||
assign SYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc;
|
||||
|
||||
assign SYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir;
|
||||
|
||||
assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af;
|
||||
|
||||
assign SYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
|
||||
|
||||
assign SYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
|
||||
|
||||
assign SYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp;
|
||||
|
||||
|
||||
reg_latch b2v_latch_af2_hi(
|
||||
.oe(SYNTHESIZED_WIRE_28),
|
||||
.we(SYNTHESIZED_WIRE_29),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_af2_lo(
|
||||
.oe(SYNTHESIZED_WIRE_30),
|
||||
.we(SYNTHESIZED_WIRE_31),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_af_hi(
|
||||
.oe(SYNTHESIZED_WIRE_32),
|
||||
.we(SYNTHESIZED_WIRE_33),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_af_lo(
|
||||
.oe(SYNTHESIZED_WIRE_34),
|
||||
.we(SYNTHESIZED_WIRE_35),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_bc2_hi(
|
||||
.oe(SYNTHESIZED_WIRE_36),
|
||||
.we(SYNTHESIZED_WIRE_37),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_bc2_lo(
|
||||
.oe(SYNTHESIZED_WIRE_38),
|
||||
.we(SYNTHESIZED_WIRE_39),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_bc_hi(
|
||||
.oe(SYNTHESIZED_WIRE_40),
|
||||
.we(SYNTHESIZED_WIRE_41),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_bc_lo(
|
||||
.oe(SYNTHESIZED_WIRE_42),
|
||||
.we(SYNTHESIZED_WIRE_43),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_de2_hi(
|
||||
.oe(SYNTHESIZED_WIRE_44),
|
||||
.we(SYNTHESIZED_WIRE_45),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_de2_lo(
|
||||
.oe(SYNTHESIZED_WIRE_46),
|
||||
.we(SYNTHESIZED_WIRE_47),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_de_hi(
|
||||
.oe(SYNTHESIZED_WIRE_48),
|
||||
.we(SYNTHESIZED_WIRE_49),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_de_lo(
|
||||
.oe(SYNTHESIZED_WIRE_50),
|
||||
.we(SYNTHESIZED_WIRE_51),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_hl2_hi(
|
||||
.oe(SYNTHESIZED_WIRE_52),
|
||||
.we(SYNTHESIZED_WIRE_53),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_hl2_lo(
|
||||
.oe(SYNTHESIZED_WIRE_54),
|
||||
.we(SYNTHESIZED_WIRE_55),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_hl_hi(
|
||||
.oe(SYNTHESIZED_WIRE_56),
|
||||
.we(SYNTHESIZED_WIRE_57),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_hl_lo(
|
||||
.oe(SYNTHESIZED_WIRE_58),
|
||||
.we(SYNTHESIZED_WIRE_59),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_ir_hi(
|
||||
.oe(SYNTHESIZED_WIRE_60),
|
||||
.we(SYNTHESIZED_WIRE_61),
|
||||
.clk(clk),
|
||||
.db(db_hi_as)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_ir_lo(
|
||||
.oe(SYNTHESIZED_WIRE_62),
|
||||
.we(SYNTHESIZED_WIRE_63),
|
||||
.clk(clk),
|
||||
.db(db_lo_as)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_ix_hi(
|
||||
.oe(SYNTHESIZED_WIRE_64),
|
||||
.we(SYNTHESIZED_WIRE_65),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_ix_lo(
|
||||
.oe(SYNTHESIZED_WIRE_66),
|
||||
.we(SYNTHESIZED_WIRE_67),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_iy_hi(
|
||||
.oe(SYNTHESIZED_WIRE_68),
|
||||
.we(SYNTHESIZED_WIRE_69),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_iy_lo(
|
||||
.oe(SYNTHESIZED_WIRE_70),
|
||||
.we(SYNTHESIZED_WIRE_71),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_pc_hi(
|
||||
.oe(SYNTHESIZED_WIRE_72),
|
||||
.we(SYNTHESIZED_WIRE_73),
|
||||
.clk(clk),
|
||||
.db(db_hi_as)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_pc_lo(
|
||||
.oe(SYNTHESIZED_WIRE_74),
|
||||
.we(SYNTHESIZED_WIRE_75),
|
||||
.clk(clk),
|
||||
.db(db_lo_as)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_sp_hi(
|
||||
.oe(SYNTHESIZED_WIRE_76),
|
||||
.we(SYNTHESIZED_WIRE_77),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_sp_lo(
|
||||
.oe(SYNTHESIZED_WIRE_78),
|
||||
.we(SYNTHESIZED_WIRE_79),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_wz_hi(
|
||||
.oe(SYNTHESIZED_WIRE_80),
|
||||
.we(SYNTHESIZED_WIRE_81),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp1)
|
||||
);
|
||||
|
||||
|
||||
reg_latch b2v_latch_wz_lo(
|
||||
.oe(SYNTHESIZED_WIRE_82),
|
||||
.we(SYNTHESIZED_WIRE_83),
|
||||
.clk(clk),
|
||||
.db(gdfx_temp0)
|
||||
);
|
||||
|
||||
assign gdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz;
|
||||
assign gdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz;
|
||||
assign gdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz;
|
||||
assign gdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz;
|
||||
assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;
|
||||
assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;
|
||||
assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;
|
||||
assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;
|
||||
|
||||
assign db_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz;
|
||||
assign db_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz;
|
||||
assign db_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz;
|
||||
assign db_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz;
|
||||
assign db_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz;
|
||||
assign db_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz;
|
||||
assign db_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz;
|
||||
assign db_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz;
|
||||
|
||||
assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;
|
||||
assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;
|
||||
assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;
|
||||
assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;
|
||||
assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;
|
||||
assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;
|
||||
assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;
|
||||
assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;
|
||||
|
||||
assign db_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz;
|
||||
assign db_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz;
|
||||
assign db_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz;
|
||||
assign db_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz;
|
||||
assign db_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz;
|
||||
assign db_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz;
|
||||
assign db_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz;
|
||||
assign db_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz;
|
||||
|
||||
assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;
|
||||
assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;
|
||||
assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;
|
||||
assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;
|
||||
assign db_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz;
|
||||
assign db_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz;
|
||||
assign db_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz;
|
||||
assign db_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz;
|
||||
|
||||
assign gdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz;
|
||||
assign gdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz;
|
||||
assign gdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz;
|
||||
assign gdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz;
|
||||
assign gdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz;
|
||||
assign gdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz;
|
||||
assign gdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz;
|
||||
assign gdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz;
|
||||
|
||||
assign db_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz;
|
||||
assign db_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz;
|
||||
assign db_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz;
|
||||
assign db_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz;
|
||||
assign db_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz;
|
||||
assign db_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz;
|
||||
assign db_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz;
|
||||
assign db_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz;
|
||||
|
||||
assign gdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz;
|
||||
assign gdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz;
|
||||
assign gdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz;
|
||||
assign gdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz;
|
||||
assign gdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz;
|
||||
assign gdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz;
|
||||
assign gdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz;
|
||||
assign gdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz;
|
||||
|
||||
|
||||
endmodule
|
||||
69
fpga/tb/az80/reg_latch.v
Normal file
69
fpga/tb/az80/reg_latch.v
Normal file
@ -0,0 +1,69 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Fri Nov 07 10:28:37 2014"
|
||||
|
||||
module reg_latch(
|
||||
we,
|
||||
oe,
|
||||
clk,
|
||||
db
|
||||
);
|
||||
|
||||
|
||||
input wire we;
|
||||
input wire oe;
|
||||
input wire clk;
|
||||
inout wire [7:0] db;
|
||||
|
||||
reg [7:0] latch;
|
||||
|
||||
|
||||
|
||||
|
||||
assign db[7] = oe ? latch[7] : 1'bz;
|
||||
assign db[6] = oe ? latch[6] : 1'bz;
|
||||
assign db[5] = oe ? latch[5] : 1'bz;
|
||||
assign db[4] = oe ? latch[4] : 1'bz;
|
||||
assign db[3] = oe ? latch[3] : 1'bz;
|
||||
assign db[2] = oe ? latch[2] : 1'bz;
|
||||
assign db[1] = oe ? latch[1] : 1'bz;
|
||||
assign db[0] = oe ? latch[0] : 1'bz;
|
||||
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if (we)
|
||||
begin
|
||||
latch[7:0] <= db[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
157
fpga/tb/az80/resets.v
Normal file
157
fpga/tb/az80/resets.v
Normal file
@ -0,0 +1,157 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Dec 10 08:57:54 2016"
|
||||
|
||||
module resets(
|
||||
reset_in,
|
||||
clk,
|
||||
M1,
|
||||
T2,
|
||||
fpga_reset,
|
||||
nhold_clk_wait,
|
||||
clrpc,
|
||||
nreset
|
||||
);
|
||||
|
||||
|
||||
input wire reset_in;
|
||||
input wire clk;
|
||||
input wire M1;
|
||||
input wire T2;
|
||||
input wire fpga_reset;
|
||||
input wire nhold_clk_wait;
|
||||
output wire clrpc;
|
||||
output wire nreset;
|
||||
|
||||
reg clrpc_int;
|
||||
wire nclk;
|
||||
reg x1;
|
||||
wire x2;
|
||||
wire x3;
|
||||
wire SYNTHESIZED_WIRE_8;
|
||||
wire SYNTHESIZED_WIRE_1;
|
||||
reg SYNTHESIZED_WIRE_9;
|
||||
reg DFFE_intr_ff3;
|
||||
reg SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
reg SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
|
||||
assign nreset = SYNTHESIZED_WIRE_6;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge nclk or negedge SYNTHESIZED_WIRE_8)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_8)
|
||||
begin
|
||||
x1 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;
|
||||
end
|
||||
end
|
||||
|
||||
assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_10;
|
||||
|
||||
assign SYNTHESIZED_WIRE_1 = ~reset_in;
|
||||
|
||||
assign x2 = x1 & SYNTHESIZED_WIRE_11;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = M1 & T2;
|
||||
|
||||
assign x3 = x1 & SYNTHESIZED_WIRE_3;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11;
|
||||
|
||||
assign nclk = ~clk;
|
||||
|
||||
assign SYNTHESIZED_WIRE_8 = ~fpga_reset;
|
||||
|
||||
|
||||
always@(posedge nclk)
|
||||
begin
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
DFFE_intr_ff3 <= SYNTHESIZED_WIRE_9;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge nclk)
|
||||
begin
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge nclk)
|
||||
begin
|
||||
if (nhold_clk_wait)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge SYNTHESIZED_WIRE_8)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_8)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_12 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_12 <= x3;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge nclk or negedge SYNTHESIZED_WIRE_6)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_6)
|
||||
begin
|
||||
clrpc_int <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
292
fpga/tb/az80/sequencer.v
Normal file
292
fpga/tb/az80/sequencer.v
Normal file
@ -0,0 +1,292 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Copyright (C) 1991-2013 Altera Corporation
|
||||
// Your use of Altera Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License
|
||||
// Subscription Agreement, Altera MegaCore Function License
|
||||
// Agreement, or other applicable license agreement, including,
|
||||
// without limitation, that your use is for the sole purpose of
|
||||
// programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the
|
||||
// applicable agreement for further details.
|
||||
|
||||
// PROGRAM "Quartus II 64-Bit"
|
||||
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
|
||||
// CREATED "Sat Feb 13 17:56:57 2016"
|
||||
|
||||
module sequencer(
|
||||
clk,
|
||||
nextM,
|
||||
setM1,
|
||||
nreset,
|
||||
hold_clk_iorq,
|
||||
hold_clk_wait,
|
||||
hold_clk_busrq,
|
||||
M1,
|
||||
M2,
|
||||
M3,
|
||||
M4,
|
||||
M5,
|
||||
T1,
|
||||
T2,
|
||||
T3,
|
||||
T4,
|
||||
T5,
|
||||
T6,
|
||||
timings_en
|
||||
);
|
||||
|
||||
|
||||
input wire clk;
|
||||
input wire nextM;
|
||||
input wire setM1;
|
||||
input wire nreset;
|
||||
input wire hold_clk_iorq;
|
||||
input wire hold_clk_wait;
|
||||
input wire hold_clk_busrq;
|
||||
output wire M1;
|
||||
output wire M2;
|
||||
output wire M3;
|
||||
output wire M4;
|
||||
output reg M5;
|
||||
output wire T1;
|
||||
output wire T2;
|
||||
output wire T3;
|
||||
output wire T4;
|
||||
output wire T5;
|
||||
output reg T6;
|
||||
output wire timings_en;
|
||||
|
||||
wire ena_M;
|
||||
wire ena_T;
|
||||
reg DFFE_M4_ff;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
reg DFFE_T1_ff;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
reg DFFE_T2_ff;
|
||||
reg DFFE_T3_ff;
|
||||
reg DFFE_T4_ff;
|
||||
reg DFFE_T5_ff;
|
||||
reg DFFE_M1_ff;
|
||||
reg DFFE_M2_ff;
|
||||
reg DFFE_M3_ff;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_10;
|
||||
wire SYNTHESIZED_WIRE_11;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_13;
|
||||
wire SYNTHESIZED_WIRE_14;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_16;
|
||||
wire SYNTHESIZED_WIRE_17;
|
||||
|
||||
assign M1 = DFFE_M1_ff;
|
||||
assign M2 = DFFE_M2_ff;
|
||||
assign M3 = DFFE_M3_ff;
|
||||
assign M4 = DFFE_M4_ff;
|
||||
assign T1 = DFFE_T1_ff;
|
||||
assign T2 = DFFE_T2_ff;
|
||||
assign T3 = DFFE_T3_ff;
|
||||
assign T4 = DFFE_T4_ff;
|
||||
assign T5 = DFFE_T5_ff;
|
||||
|
||||
|
||||
|
||||
assign ena_M = nextM | setM1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign SYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19;
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign SYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign SYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18;
|
||||
|
||||
assign ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_M1_ff <= 1;
|
||||
end
|
||||
else
|
||||
if (ena_M)
|
||||
begin
|
||||
DFFE_M1_ff <= setM1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_M2_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_M)
|
||||
begin
|
||||
DFFE_M2_ff <= SYNTHESIZED_WIRE_9;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_M3_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_M)
|
||||
begin
|
||||
DFFE_M3_ff <= SYNTHESIZED_WIRE_10;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_M4_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_M)
|
||||
begin
|
||||
DFFE_M4_ff <= SYNTHESIZED_WIRE_11;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
M5 <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_M)
|
||||
begin
|
||||
M5 <= SYNTHESIZED_WIRE_12;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = ~ena_M;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = ~setM1;
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_T1_ff <= 1;
|
||||
end
|
||||
else
|
||||
if (ena_T)
|
||||
begin
|
||||
DFFE_T1_ff <= ena_M;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_T2_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_T)
|
||||
begin
|
||||
DFFE_T2_ff <= SYNTHESIZED_WIRE_13;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_T3_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_T)
|
||||
begin
|
||||
DFFE_T3_ff <= SYNTHESIZED_WIRE_14;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_T4_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_T)
|
||||
begin
|
||||
DFFE_T4_ff <= SYNTHESIZED_WIRE_15;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
DFFE_T5_ff <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_T)
|
||||
begin
|
||||
DFFE_T5_ff <= SYNTHESIZED_WIRE_16;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge nreset)
|
||||
begin
|
||||
if (!nreset)
|
||||
begin
|
||||
T6 <= 0;
|
||||
end
|
||||
else
|
||||
if (ena_T)
|
||||
begin
|
||||
T6 <= SYNTHESIZED_WIRE_17;
|
||||
end
|
||||
end
|
||||
|
||||
assign timings_en = ena_T;
|
||||
|
||||
endmodule
|
||||
707
fpga/tb/az80/temp_wires.vh
Normal file
707
fpga/tb/az80/temp_wires.vh
Normal file
@ -0,0 +1,707 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
// Automatically generated by gencompile.py
|
||||
|
||||
reg ctl_reg_gp_sel_pla17npla50M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla17npla50M1T1_3;
|
||||
reg ctl_reg_sys_hilo_pla17npla50M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla17npla50M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla61npla58npla59M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla61npla58npla59M1T1_3;
|
||||
reg ctl_reg_gp_sel_pla61npla58npla59M1T4_3;
|
||||
reg ctl_reg_gp_hilo_pla61npla58npla59M1T4_4;
|
||||
reg ctl_reg_gp_sel_use_ixiypla58M1T1_2;
|
||||
reg ctl_reg_gp_hilo_use_ixiypla58M1T1_3;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla58M2T1_3;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla58M2T2_4;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla58M1T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla58M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla59M2T1_3;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla59M2T2_4;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla59M1T4_4;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla59M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla59M4T1_3;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4;
|
||||
reg ctl_reg_sys_hilo_pla40M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla40M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla40M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla40M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla50npla40M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla50npla40M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla50npla40M3T1_2;
|
||||
reg ctl_reg_gp_hilo_pla50npla40M3T1_3;
|
||||
reg ctl_reg_gp_sel_pla8pla13M1T4_4;
|
||||
reg ctl_reg_gp_hilo_pla8pla13M1T4_5;
|
||||
reg ctl_reg_gp_sel_pla8pla13M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla8pla13M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla8pla13M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla8npla13M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla8npla13M1T1_3;
|
||||
reg ctl_reg_gp_sel_pla8npla13M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla8npla13M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla8npla13M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M3T3_5;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M3T3_10;
|
||||
reg ctl_reg_gp_sel_pla38pla13M4T1_3;
|
||||
reg ctl_reg_gp_hilo_pla38pla13M4T1_4;
|
||||
reg ctl_reg_sys_hilo_pla38pla13M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla38npla13M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla38npla13M1T1_3;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M3T3_6;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M4T1_3;
|
||||
reg ctl_reg_sys_hilo_pla38npla13M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla83M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla83M1T1_3;
|
||||
reg ctl_pf_sel_pla83M1T1_19;
|
||||
reg ctl_reg_gp_sel_pla83M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla83M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla83M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla83M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla83M1T4_3;
|
||||
reg ctl_reg_gp_sel_pla57M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla57M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla57M1T4_4;
|
||||
reg ctl_reg_gp_sel_pla7M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla7M1T1_3;
|
||||
reg ctl_reg_sys_hilo_pla7M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla7M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla7M3T1_3;
|
||||
reg ctl_reg_gp_sel_pla7M3T1_6;
|
||||
reg ctl_reg_gp_hilo_pla7M3T1_7;
|
||||
reg ctl_reg_sys_hilo_pla7M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M3T3_5;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M3T3_10;
|
||||
reg ctl_reg_gp_sel_pla30pla13M4T1_3;
|
||||
reg ctl_reg_gp_hilo_pla30pla13M4T1_4;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M4T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M4T3_5;
|
||||
reg ctl_reg_gp_sel_pla30pla13M5T1_3;
|
||||
reg ctl_reg_gp_hilo_pla30pla13M5T1_4;
|
||||
reg ctl_reg_sys_hilo_pla30pla13M5T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M3T3_6;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M4T1_3;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla30npla13M4T3_5;
|
||||
reg ctl_reg_gp_hilo_pla30npla13M4T3_6;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M5T1_3;
|
||||
reg ctl_reg_sys_hilo_pla30npla13M5T2_4;
|
||||
reg ctl_reg_gp_sel_pla30npla13M5T3_4;
|
||||
reg ctl_reg_gp_hilo_pla30npla13M5T3_5;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M3T3_5;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M3T3_10;
|
||||
reg ctl_reg_gp_sel_pla31pla33M4T1_3;
|
||||
reg ctl_reg_gp_hilo_pla31pla33M4T1_4;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M4T2_4;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M4T3_5;
|
||||
reg ctl_reg_gp_sel_pla31pla33M5T1_3;
|
||||
reg ctl_reg_gp_hilo_pla31pla33M5T1_4;
|
||||
reg ctl_reg_sys_hilo_pla31pla33M5T2_4;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M3T3_6;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M4T1_3;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla31npla33M4T3_5;
|
||||
reg ctl_reg_gp_hilo_pla31npla33M4T3_6;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M5T1_3;
|
||||
reg ctl_reg_sys_hilo_pla31npla33M5T2_4;
|
||||
reg ctl_reg_gp_sel_pla31npla33M5T3_4;
|
||||
reg ctl_reg_gp_hilo_pla31npla33M5T3_5;
|
||||
reg ctl_reg_gp_sel_pla5M1T4_2;
|
||||
reg ctl_reg_gp_hilo_pla5M1T4_3;
|
||||
reg ctl_reg_gp_sel_pla5M1T5_2;
|
||||
reg ctl_reg_gp_hilo_pla5M1T5_3;
|
||||
reg ctl_reg_gp_sel_pla23pla16M1T5_4;
|
||||
reg ctl_reg_gp_hilo_pla23pla16M1T5_5;
|
||||
reg ctl_reg_gp_sel_pla23pla16M2T1_5;
|
||||
reg ctl_reg_gp_hilo_pla23pla16M2T1_6;
|
||||
reg ctl_reg_gp_sel_pla23pla16M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla23pla16M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla23pla16M2T3_5;
|
||||
reg ctl_reg_gp_hilo_pla23pla16M2T3_6;
|
||||
reg ctl_reg_gp_sel_pla23pla16M3T1_5;
|
||||
reg ctl_reg_gp_hilo_pla23pla16M3T1_6;
|
||||
reg ctl_reg_gp_sel_pla23pla16M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla23pla16M3T2_4;
|
||||
reg ctl_reg_gp_sel_pla23npla16M2T1_3;
|
||||
reg ctl_reg_gp_hilo_pla23npla16M2T1_4;
|
||||
reg ctl_reg_gp_sel_pla23npla16M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla23npla16M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla23npla16M2T3_5;
|
||||
reg ctl_reg_gp_hilo_pla23npla16M2T3_6;
|
||||
reg ctl_reg_gp_sel_pla23npla16M3T1_3;
|
||||
reg ctl_reg_gp_hilo_pla23npla16M3T1_4;
|
||||
reg ctl_reg_gp_sel_pla23npla16M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla23npla16M3T2_4;
|
||||
reg ctl_reg_gp_sel_pla23npla16M3T3_4;
|
||||
reg ctl_reg_gp_hilo_pla23npla16M3T3_5;
|
||||
reg ctl_reg_gp_sel_pla10M2T1_3;
|
||||
reg ctl_reg_gp_hilo_pla10M2T1_4;
|
||||
reg ctl_reg_gp_sel_pla10M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla10M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla10M2T3_6;
|
||||
reg ctl_reg_gp_sel_pla10M3T1_3;
|
||||
reg ctl_reg_gp_hilo_pla10M3T1_4;
|
||||
reg ctl_reg_gp_sel_pla10M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla10M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla10M3T3_4;
|
||||
reg ctl_reg_gp_sel_pla10M3T4_4;
|
||||
reg ctl_reg_gp_hilo_pla10M3T4_5;
|
||||
reg ctl_reg_gp_sel_pla10M4T1_5;
|
||||
reg ctl_reg_gp_hilo_pla10M4T1_6;
|
||||
reg ctl_reg_gp_sel_pla10M4T2_3;
|
||||
reg ctl_reg_gp_hilo_pla10M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla10M4T3_5;
|
||||
reg ctl_reg_gp_hilo_pla10M4T3_6;
|
||||
reg ctl_reg_gp_sel_pla10M5T1_5;
|
||||
reg ctl_reg_gp_hilo_pla10M5T1_6;
|
||||
reg ctl_reg_gp_sel_pla10M5T2_3;
|
||||
reg ctl_reg_gp_hilo_pla10M5T2_4;
|
||||
reg ctl_reg_sys_hilo_pla10M5T3_3;
|
||||
reg ctl_reg_gp_sel_pla10M5T4_2;
|
||||
reg ctl_reg_gp_hilo_pla10M5T4_3;
|
||||
reg ctl_pf_sel_pla12M1T1_12;
|
||||
reg ctl_reg_gp_sel_pla12M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla12M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla12M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla12M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla12M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla12M2T1_3;
|
||||
reg ctl_reg_gp_sel_pla12M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla12M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla12M3T1_2;
|
||||
reg ctl_reg_gp_hilo_pla12M3T1_3;
|
||||
reg ctl_reg_gp_sel_pla12M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla12M3T2_4;
|
||||
reg ctl_reg_gp_sel_pla12M3T3_2;
|
||||
reg ctl_reg_gp_hilo_pla12M3T3_3;
|
||||
reg ctl_reg_gp_sel_pla12M3T4_2;
|
||||
reg ctl_reg_gp_hilo_pla12M3T4_3;
|
||||
reg ctl_reg_sys_hilo_pla12M4T1_2;
|
||||
reg ctl_reg_sys_hilo_pla12M4T2_3;
|
||||
reg ctl_reg_sys_hilo_pla12M4T3_2;
|
||||
reg ctl_reg_sys_hilo_pla12M4T4_3;
|
||||
reg ctl_pf_sel_pla11M1T1_11;
|
||||
reg ctl_reg_gp_sel_pla11M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla11M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla11M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla11M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla11M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla11M2T1_3;
|
||||
reg ctl_reg_gp_sel_pla11M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla11M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla11M3T3_1;
|
||||
reg ctl_reg_gp_hilo_pla11M3T3_2;
|
||||
reg ctl_reg_gp_sel_pla11M3T4_2;
|
||||
reg ctl_reg_gp_hilo_pla11M3T4_3;
|
||||
reg ctl_reg_sys_hilo_pla11M4T1_2;
|
||||
reg ctl_reg_sys_hilo_pla11M4T2_3;
|
||||
reg ctl_reg_sys_hilo_pla11M4T3_2;
|
||||
reg ctl_reg_sys_hilo_pla11M4T4_3;
|
||||
reg ctl_reg_gp_sel_pla65npla52M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla65npla52M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla65npla52M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla65npla52M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla65npla52M1T4_3;
|
||||
reg ctl_reg_gp_hilo_pla65npla52M1T4_4;
|
||||
reg ctl_reg_gp_sel_pla64M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla64M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla64M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla64M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla64M1T4_4;
|
||||
reg ctl_reg_gp_hilo_pla64M1T4_5;
|
||||
reg ctl_reg_sys_hilo_pla64M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla64M2T2_4;
|
||||
reg ctl_reg_gp_sel_use_ixiypla52M1T3_1;
|
||||
reg ctl_reg_gp_hilo_use_ixiypla52M1T3_2;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla52M2T1_3;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla52M2T2_4;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla52M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla52M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla52M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla52M4T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3;
|
||||
reg ctl_reg_gp_sel_pla66npla53M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla66npla53M1T1_3;
|
||||
reg ctl_pf_sel_pla66npla53M1T1_15;
|
||||
reg ctl_reg_gp_sel_pla66npla53M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla66npla53M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla66npla53M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla66npla53M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1;
|
||||
reg ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2;
|
||||
reg ctl_reg_gp_sel_use_ixiypla53M1T3_1;
|
||||
reg ctl_reg_gp_hilo_use_ixiypla53M1T3_2;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla53M2T1_3;
|
||||
reg ctl_reg_sys_hilo_use_ixiypla53M2T2_4;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla53M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla53M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla53M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3;
|
||||
reg ctl_pf_sel_nuse_ixiypla53M2T4_14;
|
||||
reg ctl_pf_sel_nuse_ixiypla53M4T4_14;
|
||||
reg ctl_reg_gp_sel_pla69M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla69M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla69M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla69M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla69M1T4_3;
|
||||
reg ctl_reg_gp_hilo_pla69M1T4_4;
|
||||
reg ctl_reg_gp_sel_pla69M2T1_1;
|
||||
reg ctl_reg_gp_hilo_pla69M2T1_2;
|
||||
reg ctl_reg_sys_hilo_pla69M2T2_3;
|
||||
reg ctl_reg_gp_sel_pla69M2T3_1;
|
||||
reg ctl_reg_gp_hilo_pla69M2T3_2;
|
||||
reg ctl_reg_gp_sel_pla69M2T4_2;
|
||||
reg ctl_reg_gp_hilo_pla69M2T4_3;
|
||||
reg ctl_reg_sys_hilo_pla69M3T1_2;
|
||||
reg ctl_reg_sys_hilo_pla69M3T1_7;
|
||||
reg ctl_reg_gp_sel_pla69M3T2_2;
|
||||
reg ctl_reg_gp_hilo_pla69M3T2_3;
|
||||
reg ctl_reg_gp_sel_op3pla68M1T2_2;
|
||||
reg ctl_reg_gp_hilo_op3pla68M1T2_3;
|
||||
reg ctl_reg_gp_sel_op3pla68M1T3_1;
|
||||
reg ctl_reg_gp_hilo_op3pla68M1T3_2;
|
||||
reg ctl_reg_gp_sel_op3pla68M1T4_3;
|
||||
reg ctl_reg_gp_hilo_op3pla68M1T4_4;
|
||||
reg ctl_reg_gp_sel_op3pla68M2T1_1;
|
||||
reg ctl_reg_gp_hilo_op3pla68M2T1_2;
|
||||
reg ctl_reg_sys_hilo_op3pla68M2T2_3;
|
||||
reg ctl_reg_gp_sel_op3pla68M2T3_1;
|
||||
reg ctl_reg_gp_hilo_op3pla68M2T3_2;
|
||||
reg ctl_reg_gp_sel_op3pla68M2T4_2;
|
||||
reg ctl_reg_gp_hilo_op3pla68M2T4_3;
|
||||
reg ctl_reg_sys_hilo_op3pla68M3T1_2;
|
||||
reg ctl_reg_sys_hilo_op3pla68M3T1_7;
|
||||
reg ctl_pf_sel_op3pla68M3T1_18;
|
||||
reg ctl_reg_gp_sel_op3pla68M3T2_2;
|
||||
reg ctl_reg_gp_hilo_op3pla68M3T2_3;
|
||||
reg ctl_reg_gp_sel_nop3pla68M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M1T2_3;
|
||||
reg ctl_reg_gp_sel_nop3pla68M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M1T3_2;
|
||||
reg ctl_reg_gp_sel_nop3pla68M1T4_3;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M1T4_4;
|
||||
reg ctl_reg_gp_sel_nop3pla68M2T1_1;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M2T1_2;
|
||||
reg ctl_reg_sys_hilo_nop3pla68M2T2_3;
|
||||
reg ctl_reg_gp_sel_nop3pla68M2T3_1;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M2T3_2;
|
||||
reg ctl_reg_gp_sel_nop3pla68M2T4_2;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M2T4_3;
|
||||
reg ctl_reg_sys_hilo_nop3pla68M3T1_2;
|
||||
reg ctl_reg_sys_hilo_nop3pla68M3T1_7;
|
||||
reg ctl_pf_sel_nop3pla68M3T1_20;
|
||||
reg ctl_reg_gp_sel_nop3pla68M3T2_2;
|
||||
reg ctl_reg_gp_hilo_nop3pla68M3T2_3;
|
||||
reg ctl_reg_gp_sel_pla9M1T4_2;
|
||||
reg ctl_reg_gp_hilo_pla9M1T4_3;
|
||||
reg ctl_reg_gp_sel_pla9M1T5_2;
|
||||
reg ctl_reg_gp_hilo_pla9M1T5_3;
|
||||
reg ctl_reg_gp_sel_pla77M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla77M1T1_3;
|
||||
reg ctl_pf_sel_pla77M1T1_14;
|
||||
reg ctl_reg_gp_sel_pla77M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla77M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla77M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla77M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla81M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla81M1T1_3;
|
||||
reg ctl_reg_gp_sel_pla81M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla81M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla81M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla81M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla82M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla82M1T1_3;
|
||||
reg ctl_pf_sel_pla82M1T1_16;
|
||||
reg ctl_reg_gp_sel_pla82M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla82M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla82M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla82M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla89M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla89M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla89M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla89M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla92M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla92M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla92M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla92M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla25M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla25M1T1_3;
|
||||
reg ctl_reg_gp_sel_pla25M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla25M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla25M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla25M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla25M1T4_3;
|
||||
reg ctl_reg_gp_hilo_pla25M1T4_4;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3;
|
||||
reg ctl_pf_sel_nuse_ixiypla70npla55M1T1_20;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3;
|
||||
reg ctl_pf_sel_nuse_ixiypla70npla55M5T1_19;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3;
|
||||
reg ctl_pf_sel_nuse_ixiypla70pla55M3T1_19;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3;
|
||||
reg ctl_pf_sel_nuse_ixiypla70pla55M5T1_19;
|
||||
reg ctl_reg_gp_sel_pla15op3M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla15op3M1T1_3;
|
||||
reg ctl_pf_sel_pla15op3M1T1_18;
|
||||
reg ctl_reg_gp_sel_pla15op3M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla15op3M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla15op3M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla15op3M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla15op3M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla15op3M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla15op3M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla15nop3M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla15nop3M1T1_3;
|
||||
reg ctl_pf_sel_pla15nop3M1T1_18;
|
||||
reg ctl_reg_gp_sel_pla15nop3M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla15nop3M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla15nop3M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla15nop3M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla15nop3M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla15nop3M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla15nop3M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla15nop3M3T3_1;
|
||||
reg ctl_reg_gp_hilo_pla15nop3M3T3_2;
|
||||
reg ctl_pf_sel_nuse_ixiypla72npla55M1T1_10;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4;
|
||||
reg ctl_pf_sel_nuse_ixiypla72pla55M1T1_10;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2;
|
||||
reg ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2;
|
||||
reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3;
|
||||
reg ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3;
|
||||
reg ctl_reg_gp_sel_pla37npla28M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla37npla28M1T1_3;
|
||||
reg ctl_reg_sys_hilo_pla37npla28M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla37npla28M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla37npla28M3T1_2;
|
||||
reg ctl_reg_gp_hilo_pla37npla28M3T1_3;
|
||||
reg ctl_reg_gp_sel_pla27npla34M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla27npla34M1T1_3;
|
||||
reg ctl_pf_sel_pla27npla34M1T1_20;
|
||||
reg ctl_reg_gp_sel_pla27npla34M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla27npla34M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla27npla34M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla27npla34M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla27npla34M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla27npla34M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla37pla28M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla37pla28M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla37pla28M2T3_4;
|
||||
reg ctl_reg_gp_hilo_pla37pla28M2T3_5;
|
||||
reg ctl_reg_gp_sel_pla37pla28M3T1_3;
|
||||
reg ctl_reg_gp_hilo_pla37pla28M3T1_4;
|
||||
reg ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1;
|
||||
reg ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2;
|
||||
reg ctl_reg_gp_sel_pla27pla34M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla27pla34M2T1_3;
|
||||
reg ctl_pf_sel_pla91pla21M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla91pla21M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla91pla21M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla91pla21M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M2T1_3;
|
||||
reg ctl_reg_gp_sel_pla91pla21M2T2_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M2T2_3;
|
||||
reg ctl_reg_gp_sel_pla91pla21M2T3_3;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M2T3_4;
|
||||
reg ctl_reg_gp_sel_pla91pla21M3T1_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M3T1_3;
|
||||
reg ctl_reg_gp_sel_pla91pla21M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla91pla21M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla91pla21M4T1_2;
|
||||
reg ctl_reg_sys_hilo_pla91pla21M4T2_3;
|
||||
reg ctl_reg_sys_hilo_pla91pla21M4T3_2;
|
||||
reg ctl_reg_sys_hilo_pla91pla21M4T4_3;
|
||||
reg ctl_pf_sel_pla91pla20M1T1_9;
|
||||
reg ctl_reg_gp_sel_pla91pla20M1T2_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M1T2_3;
|
||||
reg ctl_reg_gp_sel_pla91pla20M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla91pla20M1T4_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M1T4_3;
|
||||
reg ctl_reg_gp_sel_pla91pla20M1T5_4;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M1T5_5;
|
||||
reg ctl_reg_gp_sel_pla91pla20M2T1_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M2T1_3;
|
||||
reg ctl_reg_gp_sel_pla91pla20M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla91pla20M2T3_4;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M2T3_5;
|
||||
reg ctl_reg_gp_sel_pla91pla20M3T1_2;
|
||||
reg ctl_reg_gp_hilo_pla91pla20M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla91pla20M4T1_2;
|
||||
reg ctl_reg_sys_hilo_pla91pla20M4T2_3;
|
||||
reg ctl_reg_sys_hilo_pla91pla20M4T3_2;
|
||||
reg ctl_reg_sys_hilo_pla91pla20M4T4_3;
|
||||
reg ctl_reg_sys_hilo_pla29M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla29M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla29M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla29M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla29M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla29M3T3_4;
|
||||
reg ctl_reg_sys_hilo_pla29M3T3_9;
|
||||
reg ctl_reg_gp_sel_pla43M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla43M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla43M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla43M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla43M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla43M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla43M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla43M3T3_5;
|
||||
reg ctl_reg_sys_hilo_pla43M3T3_10;
|
||||
reg ctl_reg_gp_sel_pla47M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla47M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla47M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla47M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla47M3T2_2;
|
||||
reg ctl_reg_sys_hilo_pla47M3T3_3;
|
||||
reg ctl_reg_sys_hilo_pla47M3T4_2;
|
||||
reg ctl_reg_sys_hilo_pla47M3T5_3;
|
||||
reg ctl_reg_sys_hilo_pla47M3T5_8;
|
||||
reg ctl_reg_gp_sel_pla48M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla48M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla48M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla48M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla48M3T2_2;
|
||||
reg ctl_reg_sys_hilo_pla48M3T3_3;
|
||||
reg ctl_reg_sys_hilo_pla48M3T4_2;
|
||||
reg ctl_reg_sys_hilo_pla48M3T5_3;
|
||||
reg ctl_reg_sys_hilo_pla48M3T5_8;
|
||||
reg ctl_reg_gp_sel_pla6M1T4_3;
|
||||
reg ctl_reg_gp_hilo_pla6M1T4_4;
|
||||
reg ctl_reg_gp_sel_pla26M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla26M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla26M1T4_2;
|
||||
reg ctl_reg_gp_hilo_pla26M1T4_3;
|
||||
reg ctl_reg_gp_sel_pla26M1T5_4;
|
||||
reg ctl_reg_gp_hilo_pla26M1T5_5;
|
||||
reg ctl_reg_sys_hilo_pla26M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla26M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla26M3T2_2;
|
||||
reg ctl_reg_sys_hilo_pla26M3T3_3;
|
||||
reg ctl_reg_sys_hilo_pla26M3T4_2;
|
||||
reg ctl_reg_sys_hilo_pla26M3T5_3;
|
||||
reg ctl_reg_sys_hilo_pla26M3T5_8;
|
||||
reg ctl_reg_sys_hilo_pla24M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla24M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla24M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla24M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla24M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla24M3T3_4;
|
||||
reg ctl_reg_gp_sel_pla24M3T4_4;
|
||||
reg ctl_reg_gp_hilo_pla24M3T4_5;
|
||||
reg ctl_reg_sys_hilo_pla24M4T1_6;
|
||||
reg ctl_reg_gp_sel_pla24M4T2_3;
|
||||
reg ctl_reg_gp_hilo_pla24M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla24M4T3_5;
|
||||
reg ctl_reg_gp_hilo_pla24M4T3_6;
|
||||
reg ctl_reg_sys_hilo_pla24M5T1_6;
|
||||
reg ctl_reg_gp_sel_pla24M5T2_3;
|
||||
reg ctl_reg_gp_hilo_pla24M5T2_4;
|
||||
reg ctl_reg_sys_hilo_pla24M5T3_4;
|
||||
reg ctl_reg_gp_sel_pla42M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla42M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla42M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla42M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla42M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla42M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla42M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla42M3T3_6;
|
||||
reg ctl_reg_gp_sel_pla42M3T4_4;
|
||||
reg ctl_reg_gp_hilo_pla42M3T4_5;
|
||||
reg ctl_reg_sys_hilo_pla42M4T1_6;
|
||||
reg ctl_reg_gp_sel_pla42M4T2_3;
|
||||
reg ctl_reg_gp_hilo_pla42M4T2_4;
|
||||
reg ctl_reg_gp_sel_pla42M4T3_5;
|
||||
reg ctl_reg_gp_hilo_pla42M4T3_6;
|
||||
reg ctl_reg_sys_hilo_pla42M5T1_6;
|
||||
reg ctl_reg_gp_sel_pla42M5T2_3;
|
||||
reg ctl_reg_gp_hilo_pla42M5T2_4;
|
||||
reg ctl_reg_sys_hilo_pla42M5T3_4;
|
||||
reg ctl_reg_gp_sel_pla35M2T1_3;
|
||||
reg ctl_reg_gp_hilo_pla35M2T1_4;
|
||||
reg ctl_reg_gp_sel_pla35M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla35M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla35M2T3_6;
|
||||
reg ctl_reg_gp_sel_pla35M3T1_3;
|
||||
reg ctl_reg_gp_hilo_pla35M3T1_4;
|
||||
reg ctl_reg_gp_sel_pla35M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla35M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla35M3T3_4;
|
||||
reg ctl_reg_sys_hilo_pla35M3T3_9;
|
||||
reg ctl_reg_gp_sel_pla45M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla45M1T3_2;
|
||||
reg ctl_reg_gp_sel_pla45M2T1_3;
|
||||
reg ctl_reg_gp_hilo_pla45M2T1_4;
|
||||
reg ctl_reg_gp_sel_pla45M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla45M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla45M2T3_6;
|
||||
reg ctl_reg_gp_sel_pla45M3T1_3;
|
||||
reg ctl_reg_gp_hilo_pla45M3T1_4;
|
||||
reg ctl_reg_gp_sel_pla45M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla45M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla45M3T3_4;
|
||||
reg ctl_reg_sys_hilo_pla45M3T3_9;
|
||||
reg ctl_reg_gp_sel_pla46M2T1_3;
|
||||
reg ctl_reg_gp_hilo_pla46M2T1_4;
|
||||
reg ctl_reg_gp_sel_pla46M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla46M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla46M2T3_6;
|
||||
reg ctl_reg_gp_sel_pla46M3T1_3;
|
||||
reg ctl_reg_gp_hilo_pla46M3T1_4;
|
||||
reg ctl_reg_gp_sel_pla46M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla46M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla46M3T3_4;
|
||||
reg ctl_reg_sys_hilo_pla46M3T3_9;
|
||||
reg ctl_reg_sys_hilo_pla56M1T3_3;
|
||||
reg ctl_reg_gp_sel_pla56M1T5_4;
|
||||
reg ctl_reg_gp_hilo_pla56M1T5_5;
|
||||
reg ctl_reg_sys_hilo_pla56M2T1_6;
|
||||
reg ctl_reg_gp_sel_pla56M2T2_3;
|
||||
reg ctl_reg_gp_hilo_pla56M2T2_4;
|
||||
reg ctl_reg_gp_sel_pla56M2T3_5;
|
||||
reg ctl_reg_gp_hilo_pla56M2T3_6;
|
||||
reg ctl_reg_sys_hilo_pla56M3T1_6;
|
||||
reg ctl_reg_gp_sel_pla56M3T2_3;
|
||||
reg ctl_reg_gp_hilo_pla56M3T2_4;
|
||||
reg ctl_reg_sys_hilo_pla56M3T3_6;
|
||||
reg ctl_reg_sys_hilo_pla56M4T1_3;
|
||||
reg ctl_reg_sys_hilo_pla56M4T3_6;
|
||||
reg ctl_reg_sys_hilo_pla56M5T1_3;
|
||||
reg ctl_reg_sys_hilo_pla56M5T3_4;
|
||||
reg ctl_reg_sys_hilo_pla56M5T3_9;
|
||||
reg ctl_reg_gp_sel_pla49M1T3_1;
|
||||
reg ctl_reg_gp_hilo_pla49M1T3_2;
|
||||
reg ctl_reg_sys_hilo_pla49M2T1_3;
|
||||
reg ctl_reg_sys_hilo_pla49M2T2_4;
|
||||
reg ctl_reg_sys_hilo_pla49M3T1_3;
|
||||
reg ctl_reg_sys_hilo_pla49M3T2_4;
|
||||
reg ctl_pf_sel_pla76M1T1_2;
|
||||
reg ctl_reg_gp_sel_pla78M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla78M1T1_3;
|
||||
reg ctl_pf_sel_pla78M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla79M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla79M1T1_3;
|
||||
reg ctl_pf_sel_pla79M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla80M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla80M1T1_3;
|
||||
reg ctl_pf_sel_pla80M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla84M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla84M1T1_3;
|
||||
reg ctl_pf_sel_pla84M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla85M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla85M1T1_3;
|
||||
reg ctl_pf_sel_pla85M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla86M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla86M1T1_3;
|
||||
reg ctl_pf_sel_pla86M1T1_8;
|
||||
reg ctl_reg_gp_sel_pla88M1T1_2;
|
||||
reg ctl_reg_gp_hilo_pla88M1T1_3;
|
||||
reg ctl_pf_sel_pla88M1T1_8;
|
||||
reg ctl_reg_gp_sel_ixy_dT2_1;
|
||||
reg ctl_reg_gp_hilo_ixy_dT2_2;
|
||||
reg ctl_reg_sys_hilo_ixy_dT3_3;
|
||||
reg ctl_reg_gp_sel_ixy_dT4_1;
|
||||
reg ctl_reg_gp_hilo_ixy_dT4_2;
|
||||
reg ctl_reg_sys_hilo_ixy_dT5_2;
|
||||
reg ctl_reg_sys_hilo_ixy_dT5_7;
|
||||
reg ctl_reg_sys_hilo_1M1T1_3;
|
||||
reg ctl_reg_sys_hilo_1M1T2_2;
|
||||
reg ctl_reg_sys_hilo_1M1T3_3;
|
||||
reg ctl_reg_sys_hilo_setM1_2;
|
||||
98
fpga/tb/az80/z80_top_direct_n.v
Normal file
98
fpga/tb/az80/z80_top_direct_n.v
Normal file
@ -0,0 +1,98 @@
|
||||
//----------------------------------------------------------------------------
|
||||
// A-Z80 CPU Copyright (C) 2014,2016 Goran Devic, www.baltazarstudios.com
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//----------------------------------------------------------------------------
|
||||
//============================================================================
|
||||
// Z80 Top level using the direct module declaration
|
||||
//============================================================================
|
||||
`timescale 1us/ 100 ns
|
||||
|
||||
module z80_top_direct_n(
|
||||
output wire nM1,
|
||||
output wire nMREQ,
|
||||
output wire nIORQ,
|
||||
output wire nRD,
|
||||
output wire nWR,
|
||||
output wire nRFSH,
|
||||
output wire nHALT,
|
||||
output wire nBUSACK,
|
||||
|
||||
input wire nWAIT,
|
||||
input wire nINT,
|
||||
input wire nNMI,
|
||||
input wire nRESET,
|
||||
input wire nBUSRQ,
|
||||
|
||||
input wire CLK,
|
||||
output wire [15:0] A,
|
||||
inout wire [7:0] D
|
||||
);
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Include core A-Z80 level connecting all internal modules
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
`include "core.vh"
|
||||
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
// Address, Data and Control bus drivers connecting to external pins
|
||||
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
address_pins address_pins_(
|
||||
.clk (clk),
|
||||
.bus_ab_pin_we (bus_ab_pin_we),
|
||||
.pin_control_oe (pin_control_oe),
|
||||
.address (address),
|
||||
.abus (A)
|
||||
);
|
||||
|
||||
data_pins data_pins_(
|
||||
.bus_db_pin_oe (bus_db_pin_oe),
|
||||
.bus_db_pin_re (bus_db_pin_re),
|
||||
.ctl_bus_db_we (ctl_bus_db_we),
|
||||
.ctl_bus_db_oe (ctl_bus_db_oe),
|
||||
.clk (clk),
|
||||
.db (db0),
|
||||
.D (D)
|
||||
);
|
||||
|
||||
control_pins_n control_pins_(
|
||||
.busack (busack),
|
||||
.CPUCLK (CLK),
|
||||
.pin_control_oe(pin_control_oe),
|
||||
.in_halt (in_halt),
|
||||
.pin_nWAIT (nWAIT),
|
||||
.pin_nBUSRQ (nBUSRQ),
|
||||
.pin_nINT (nINT),
|
||||
.pin_nNMI (nNMI),
|
||||
.pin_nRESET (nRESET),
|
||||
.nM1_out (nM1_out),
|
||||
.nRFSH_out (nRFSH_out),
|
||||
.nRD_out (nRD_out),
|
||||
.nWR_out (nWR_out),
|
||||
.nIORQ_out (nIORQ_out),
|
||||
.nMREQ_out (nMREQ_out),
|
||||
.nmi (nmi),
|
||||
.busrq (busrq),
|
||||
.clk (clk),
|
||||
.intr (intr),
|
||||
.mwait (mwait),
|
||||
.reset_in (reset_in),
|
||||
.pin_nM1 (nM1),
|
||||
.pin_nMREQ (nMREQ),
|
||||
.pin_nIORQ (nIORQ),
|
||||
.pin_nRD (nRD),
|
||||
.pin_nWR (nWR),
|
||||
.pin_nRFSH (nRFSH),
|
||||
.pin_nHALT (nHALT),
|
||||
.pin_nBUSACK (nBUSACK)
|
||||
);
|
||||
|
||||
endmodule
|
||||
58
fpga/tb/rom.asm
Normal file
58
fpga/tb/rom.asm
Normal file
@ -0,0 +1,58 @@
|
||||
DEVICE ZXSPECTRUM48
|
||||
|
||||
ORG #0000
|
||||
Start:
|
||||
jp Main
|
||||
|
||||
ORG #0038
|
||||
Int1:
|
||||
jp #1ff8
|
||||
ORG #00FF
|
||||
DB #38
|
||||
|
||||
ORG #0066
|
||||
Nmi:
|
||||
jp #1ffa
|
||||
push af
|
||||
ld a, #08
|
||||
out (#ff), a
|
||||
pop af
|
||||
retn
|
||||
|
||||
ORG #1000
|
||||
Main:
|
||||
im 2
|
||||
ei
|
||||
|
||||
ld bc, #7ffd
|
||||
ld a, #11
|
||||
out (c), a
|
||||
|
||||
//.72 nop
|
||||
//ld a, 7
|
||||
//out (#fe), a
|
||||
|
||||
//ld hl, #4000
|
||||
//ld de, #c000
|
||||
//ld bc, 100
|
||||
//ldir
|
||||
|
||||
//ld c, #ff
|
||||
//ld b, #ff
|
||||
//ld hl, #4000
|
||||
//otir
|
||||
|
||||
jp #1fff
|
||||
|
||||
ORG #1FF8
|
||||
reti
|
||||
ORG #1FFA
|
||||
retn
|
||||
ORG #1FFF
|
||||
jp #3d00
|
||||
|
||||
Loop:
|
||||
halt
|
||||
jp Loop
|
||||
|
||||
SAVEBIN "rom.bin",0,16384
|
||||
24
fpga/tb/stubs/asmi.v
Normal file
24
fpga/tb/stubs/asmi.v
Normal file
@ -0,0 +1,24 @@
|
||||
module asmi (
|
||||
addr,
|
||||
clkin,
|
||||
rden,
|
||||
read,
|
||||
reset,
|
||||
busy,
|
||||
data_valid,
|
||||
dataout)/* synthesis synthesis_clearbox = 2 */;
|
||||
|
||||
input [23:0] addr;
|
||||
input clkin;
|
||||
input rden;
|
||||
input read;
|
||||
input reset;
|
||||
output busy;
|
||||
output data_valid;
|
||||
output [7:0] dataout;
|
||||
|
||||
assign busy = 0;
|
||||
assign data_valid = 1'b1;
|
||||
assign dataout = 0;
|
||||
|
||||
endmodule
|
||||
21
fpga/tb/stubs/pll.v
Normal file
21
fpga/tb/stubs/pll.v
Normal file
@ -0,0 +1,21 @@
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output reg locked;
|
||||
|
||||
initial begin
|
||||
locked = 0;
|
||||
#3000 locked = 1;
|
||||
end
|
||||
|
||||
assign c0 = 0;
|
||||
assign c1 = 0;
|
||||
|
||||
endmodule
|
||||
28
fpga/tb/stubs/rom2ram.v
Normal file
28
fpga/tb/stubs/rom2ram.v
Normal file
@ -0,0 +1,28 @@
|
||||
module rom2ram (
|
||||
clock,
|
||||
datain,
|
||||
init,
|
||||
rom_data_ready,
|
||||
dataout,
|
||||
init_busy,
|
||||
ram_address,
|
||||
ram_wren,
|
||||
rom_address,
|
||||
rom_rden);
|
||||
|
||||
input clock;
|
||||
input [7:0] datain;
|
||||
input init;
|
||||
input rom_data_ready;
|
||||
output [7:0] dataout;
|
||||
output init_busy;
|
||||
output [16:0] ram_address;
|
||||
output ram_wren;
|
||||
output [16:0] rom_address;
|
||||
output rom_rden;
|
||||
|
||||
assign init_busy = 0;
|
||||
assign ram_wren = 0;
|
||||
assign rom_rden = 0;
|
||||
|
||||
endmodule
|
||||
1753
fpga/tb/t80/t80n.vhd
Normal file
1753
fpga/tb/t80/t80n.vhd
Normal file
File diff suppressed because it is too large
Load Diff
364
fpga/tb/t80/t80n_alu.vhd
Normal file
364
fpga/tb/t80/t80n_alu.vhd
Normal file
@ -0,0 +1,364 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- Modifications for the ZX Spectrum Next Project
|
||||
-- Copyright 2020 Fabio Belavenuto, Victor Trucco, Charlie Ingley, Garry Lancaster, ACX
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
-- This file is part of the ZX Spectrum Next Project
|
||||
-- <https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/tree/master/cores>
|
||||
--
|
||||
-- Modifications for the ZX Spectrum Next were made by:
|
||||
--
|
||||
-- Fabio Belavenuto : partial fix of wait bug
|
||||
-- Victor Trucco, Fabio Belavenuto, Garry Lancaster : additional instructions
|
||||
-- Charlie Ingley : complete fix of wait logic
|
||||
-- ACX : implement undocumented flags for SLI r,(IY+s)
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80N_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80N_ALU;
|
||||
|
||||
architecture rtl of T80N_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
|
||||
end;
|
||||
2582
fpga/tb/t80/t80n_mcode.vhd
Normal file
2582
fpga/tb/t80/t80n_mcode.vhd
Normal file
File diff suppressed because it is too large
Load Diff
263
fpga/tb/t80/t80n_pack.vhd
Normal file
263
fpga/tb/t80/t80n_pack.vhd
Normal file
@ -0,0 +1,263 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- Modifications for the ZX Spectrum Next Project
|
||||
-- Copyright 2020 Fabio Belavenuto, Victor Trucco, Charlie Ingley, Garry Lancaster, ACX
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
-- This file is part of the ZX Spectrum Next Project
|
||||
-- <https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/tree/master/cores>
|
||||
--
|
||||
-- Modifications for the ZX Spectrum Next were made by:
|
||||
--
|
||||
-- Fabio Belavenuto : partial fix of wait bug
|
||||
-- Victor Trucco, Fabio Belavenuto, Garry Lancaster : additional instructions
|
||||
-- Charlie Ingley : complete fix of wait logic
|
||||
-- ACX : implement undocumented flags for SLI r,(IY+s)
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.std_logic_vector;
|
||||
|
||||
package Z80N_pack is
|
||||
type Z80N_seq is ( NONE, MMU, NEXTREGW, MUL_DE, ADD_HL_A, ADD_DE_A, ADD_BC_A, SWAPNIB_A, PIXELDN, SET_A_E, PIXELAD, MIRROR_A, PUSH_nn, LDPIRX, ADD_HL_nn , ADD_DE_nn , ADD_BC_nn,
|
||||
LDIRSCALE,
|
||||
BSLA_DE_B, BSRA_DE_B, BSRL_DE_B, BSRF_DE_B, BRLC_DE_B,
|
||||
JP_C);
|
||||
signal Z80N_seq_s : Z80N_seq;
|
||||
end package;
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use work.Z80N_pack.all;
|
||||
|
||||
package T80N_Pack is
|
||||
|
||||
|
||||
|
||||
component T80N
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic;
|
||||
-- extended functions
|
||||
Z80N_dout_o : out std_logic := '0';
|
||||
Z80N_data_o : out std_logic_vector(15 downto 0);
|
||||
Z80N_command_o : out Z80N_seq
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80N_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0);
|
||||
|
||||
--extended
|
||||
reg_wr_i : in std_logic_vector(5 downto 0) := (others=>'0');
|
||||
reg_BC_i : in std_logic_vector(15 downto 0);
|
||||
reg_HL_i : in std_logic_vector(15 downto 0);
|
||||
reg_DE_i : in std_logic_vector(15 downto 0);
|
||||
reg_BC_o : out std_logic_vector(15 downto 0);
|
||||
reg_HL_o : out std_logic_vector(15 downto 0);
|
||||
reg_DE_o : out std_logic_vector(15 downto 0)
|
||||
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80N_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
XY_State : in std_logic_vector(1 downto 0);
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
XYbit_undoc : out std_logic;
|
||||
|
||||
-- entended functions
|
||||
ext_ACC_i : in std_logic_vector(7 downto 0);
|
||||
ext_Data_i : in std_logic_vector(7 downto 0);
|
||||
|
||||
Z80N_dout_o : out std_logic := '0';
|
||||
Z80N_data_o : out std_logic_vector(15 downto 0);
|
||||
Z80N_command_o : out Z80N_seq
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80N_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
|
||||
end;
|
||||
342
fpga/tb/t80/t80na.vhd
Normal file
342
fpga/tb/t80/t80na.vhd
Normal file
@ -0,0 +1,342 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core, asynchronous top level
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- Modifications for the ZX Spectrum Next Project
|
||||
-- Copyright 2020 Fabio Belavenuto, Victor Trucco, Charlie Ingley, Garry Lancaster, ACX
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please make sure that
|
||||
-- this is not a derivative work and that you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- <http://www.opencores.org/cvsweb.shtml/t80/>
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0208 : First complete release
|
||||
--
|
||||
-- 0211 : Fixed interrupt cycle
|
||||
--
|
||||
-- 0235 : Updated for T80 interface change
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
-- 0247 : Fixed bus req/ack cycle
|
||||
--
|
||||
|
||||
-- This file is part of the ZX Spectrum Next Project
|
||||
-- <https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/tree/master/cores>
|
||||
--
|
||||
-- Modifications for the ZX Spectrum Next were made by:
|
||||
--
|
||||
-- Fabio Belavenuto : partial fix of wait bug
|
||||
-- Victor Trucco, Fabio Belavenuto, Garry Lancaster : additional instructions
|
||||
-- Charlie Ingley : complete fix of wait logic
|
||||
-- ACX : implement undocumented flags for SLI r,(IY+s)
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80N_Pack.all;
|
||||
use work.Z80N_pack.all;
|
||||
|
||||
entity T80Na is
|
||||
|
||||
generic(
|
||||
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
-- D : inout std_logic_vector( 7 downto 0);
|
||||
D_i : in std_logic_vector( 7 downto 0);
|
||||
D_o : out std_logic_vector( 7 downto 0);
|
||||
|
||||
-- extended functions
|
||||
Z80N_dout_o : out std_logic := '0';
|
||||
Z80N_data_o : out std_logic_vector(15 downto 0);
|
||||
Z80N_command_o : out Z80N_seq
|
||||
);
|
||||
end T80Na;
|
||||
|
||||
|
||||
architecture rtl of T80Na is
|
||||
|
||||
signal CEN : std_logic;
|
||||
signal Reset_s : std_logic;
|
||||
signal IntCycle_n : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal MREQ : std_logic;
|
||||
signal MReq_Inhibit : std_logic;
|
||||
signal Req_Inhibit : std_logic;
|
||||
signal RD : std_logic;
|
||||
signal MREQ_n_i : std_logic;
|
||||
signal MREQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add MREQ control
|
||||
signal IORQ_n_i : std_logic;
|
||||
signal IORQ_t1 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
|
||||
signal IORQ_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
|
||||
signal IORQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
|
||||
signal IORQ_int : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ interrupt control
|
||||
signal RD_n_i : std_logic;
|
||||
signal WR_n_i : std_logic;
|
||||
signal WR_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add WR control
|
||||
signal RFSH_n_i : std_logic;
|
||||
signal BUSAK_n_i : std_logic;
|
||||
signal A_i : std_logic_vector(15 downto 0);
|
||||
signal DO : std_logic_vector(7 downto 0);
|
||||
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
CEN <= '1';
|
||||
|
||||
BUSAK_n <= BUSAK_n_i; -- 30/10/19 Charlie Ingley - IORQ/RD/WR changes
|
||||
MREQ_rw <= MREQ and (Req_Inhibit or MReq_Inhibit); -- added MREQ timing control
|
||||
MREQ_n_i <= not MREQ_rw; -- changed MREQ generation
|
||||
IORQ_rw <= IORQ and not (IORQ_t1 or IORQ_t2); -- added IORQ generation timing control
|
||||
IORQ_n_i <= not (IORQ_int or IORQ_rw); -- changed IORQ generation
|
||||
RD_n_i <= not (RD and (MREQ_rw or IORQ_rw)); -- changed RD/IORQ generation
|
||||
WR_n_i <= not (Write and ((WR_t2 and MREQ_rw) or IORQ_rw)); -- added WR/IORQ timing control
|
||||
|
||||
-- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
-- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
-- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
-- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
-- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
-- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
|
||||
-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
|
||||
|
||||
MREQ_n <= MREQ_n_i;
|
||||
IORQ_n <= IORQ_n_i;
|
||||
RD_n <= RD_n_i;
|
||||
WR_n <= WR_n_i;
|
||||
RFSH_n <= RFSH_n_i;
|
||||
A <= A_i;
|
||||
D_o <= DO;
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
Reset_s <= '0';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
Reset_s <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
z80n : T80N
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => 1)
|
||||
port map(
|
||||
CEN => CEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n_i,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => Reset_s,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n_i,
|
||||
CLK_n => CLK_n,
|
||||
A => A_i,
|
||||
-- DInst => D,
|
||||
DInst => D_i,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n,
|
||||
|
||||
Z80N_dout_o => Z80N_dout_o,
|
||||
Z80N_data_o => Z80N_data_o,
|
||||
Z80N_command_o => Z80N_command_o
|
||||
);
|
||||
|
||||
process (CLK_n)
|
||||
begin
|
||||
if CLK_n'event and CLK_n = '0' then
|
||||
if TState = "011" and BUSAK_n_i = '1' then
|
||||
-- DI_Reg <= to_x01(D);
|
||||
DI_Reg <= D_i;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- 30/10/19 Charlie Ingley - Generate WR_t2 to correct MREQ/WR timing
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
WR_t2 <= '0';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if MCycle /= "001" then
|
||||
if TState = "010" then -- WR starts on falling edge of T2 for MREQ
|
||||
WR_t2 <= Write;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "011" then -- end WR
|
||||
WR_t2 <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Generate Req_Inhibit
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
Req_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
|
||||
Req_Inhibit <= '0';
|
||||
else
|
||||
Req_Inhibit <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Generate MReq_Inhibit
|
||||
process (Reset_s, CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
MReq_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
|
||||
MReq_Inhibit <= '0';
|
||||
else
|
||||
MReq_Inhibit <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Generate RD for MREQ
|
||||
process(Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
RD <= '0';
|
||||
MREQ <= '0';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if MCycle = "001" then
|
||||
if TState = "001" then
|
||||
RD <= IntCycle_n;
|
||||
MREQ <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
RD <= '0';
|
||||
MREQ <= '1';
|
||||
end if;
|
||||
if TState = "100" then
|
||||
MREQ <= '0';
|
||||
end if;
|
||||
else
|
||||
if TState = "001" and NoRead = '0' then
|
||||
RD <= not Write;
|
||||
MREQ <= not IORQ;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
RD <= '0';
|
||||
MREQ <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- 30/10/19 Charlie Ingley - Generate IORQ_int for IORQ interrupt timing control
|
||||
process(Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
IORQ_int <= '0';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if MCycle = "001" then
|
||||
if TState = "001" then
|
||||
IORQ_int <= not IntCycle_n;
|
||||
end if;
|
||||
if TState = "010" then
|
||||
IORQ_int <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- 30/10/19 Charlie Ingley - Generate IORQ_t1 for IORQ timing control
|
||||
process(Reset_s, CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
IORQ_t1 <= '1';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if TState = "001" then
|
||||
IORQ_t1 <= not IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
IORQ_t1 <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- 30/10/19 Charlie Ingley - Generate IORQ_t2 for IORQ timing control
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
IORQ_t2 <= '1';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
IORQ_t2 <= IORQ_t1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
197
fpga/tb/testbench_zx_ula.v
Normal file
197
fpga/tb/testbench_zx_ula.v
Normal file
@ -0,0 +1,197 @@
|
||||
`timescale 100ps/10ps
|
||||
module testbench_zx_ula();
|
||||
|
||||
reg rst_n;
|
||||
reg clk28;
|
||||
|
||||
|
||||
/* CPU */
|
||||
wire rstcpu_n;
|
||||
wire [15:0] a_cpu, a_cpu_cpu;
|
||||
wire [7:0] d_cpu_o, d_cpu_i;
|
||||
wire n_rd, n_rd_cpu;
|
||||
wire n_wr, n_wr_cpu;
|
||||
wire n_iorq, n_iorq_cpu;
|
||||
wire n_mreq, n_mreq_cpu;
|
||||
wire n_m1, n_m1_cpu;
|
||||
wire n_rfsh, n_rfsh_cpu;
|
||||
wire n_int;
|
||||
wire n_nmi;
|
||||
|
||||
T80na cpu1(
|
||||
.RESET_n(rstcpu_n),
|
||||
.CLK_n(clkcpu),
|
||||
.WAIT_n(1'b1),
|
||||
.INT_n(n_int),
|
||||
.NMI_n(n_nmi),
|
||||
.BUSRQ_n(1'b1),
|
||||
.M1_n(n_m1_cpu),
|
||||
.MREQ_n(n_mreq_cpu),
|
||||
.IORQ_n(n_iorq_cpu),
|
||||
.RD_n(n_rd_cpu),
|
||||
.WR_n(n_wr_cpu),
|
||||
.RFSH_n(n_rfsh_cpu),
|
||||
.HALT_n(),
|
||||
.BUSAK_n(),
|
||||
.A(a_cpu_cpu),
|
||||
.D_i(d_cpu_i),
|
||||
.D_o(d_cpu_o)
|
||||
);
|
||||
|
||||
// z80_top_direct_n cpu1(
|
||||
// .nM1(n_m1_cpu),
|
||||
// .nMREQ(n_mreq_cpu),
|
||||
// .nIORQ(n_iorq_cpu),
|
||||
// .nRD(n_rd_cpu),
|
||||
// .nWR(n_wr_cpu),
|
||||
// .nRFSH(n_rfsh_cpu),
|
||||
// .nWAIT(1'b1),
|
||||
// .nINT(n_int),
|
||||
// .nNMI(n_nmi),
|
||||
// .nRESET(rstcpu_n),
|
||||
// .nBUSRQ(1'b1),
|
||||
// .CLK(clkcpu),
|
||||
// .A(a_cpu_cpu),
|
||||
// .D(d_cpu_o)
|
||||
// );
|
||||
// assign d_cpu_o = n_wr? d_cpu_i : {8{1'bz}};
|
||||
|
||||
|
||||
/* ULA */
|
||||
wire [7:0] vd;
|
||||
wire [18:0] va;
|
||||
wire [16:14] ra;
|
||||
wire m_romcs;
|
||||
wire n_vrd;
|
||||
wire n_vwr;
|
||||
wire dout;
|
||||
wire vdout;
|
||||
wire n_iorqge;
|
||||
reg n_magic;
|
||||
wire sd_mosi_miso;
|
||||
zx_ula zx_ula1(
|
||||
.clk_in(clk28),
|
||||
.clkcpu(clkcpu),
|
||||
.n_rstcpu(rstcpu_n),
|
||||
.a(a_cpu[15:13]),
|
||||
.vd(vd),
|
||||
.va(va),
|
||||
.n_vrd(n_vrd),
|
||||
.n_vwr(n_vwr),
|
||||
.n_rd(n_rd),
|
||||
.n_wr(n_wr),
|
||||
.n_mreq(n_mreq),
|
||||
.n_iorq(n_iorq),
|
||||
.n_m1(n_m1),
|
||||
.n_rfsh(n_rfsh),
|
||||
.n_int(n_int),
|
||||
.n_nmi(n_nmi),
|
||||
.sd_cd(1'b1),
|
||||
.sd_cs(),
|
||||
.sd_sck(),
|
||||
.sd_mosi(sd_mosi_miso),
|
||||
.sd_miso_tape_in(sd_mosi_miso),
|
||||
.ps2_clk(),
|
||||
.ps2_dat(),
|
||||
.csync(),
|
||||
.luma(),
|
||||
.chroma(),
|
||||
.snd_l(),
|
||||
.snd_r()
|
||||
);
|
||||
|
||||
|
||||
/* MEMORY */
|
||||
reg [7:0] ram [0:524288];
|
||||
wire [18:0] ram_addr_a = va;
|
||||
reg [18:0] ram_addr_a0;
|
||||
wire [7:0] ram_q_a = ram[ram_addr_a0];
|
||||
|
||||
always @(posedge clk28) begin
|
||||
if (n_vwr == 0) begin
|
||||
ram[ram_addr_a] <= vd;
|
||||
end
|
||||
ram_addr_a0 <= ram_addr_a;
|
||||
end
|
||||
initial begin
|
||||
integer i;
|
||||
for (i = 16*1024; i < 524288; i++)
|
||||
ram[i] <= 0;
|
||||
$readmemh("rom.mem", ram);
|
||||
end
|
||||
|
||||
|
||||
/* BUS ARBITER */
|
||||
assign (weak0, weak1) va[15:0] = a_cpu;
|
||||
assign vd = ~n_vrd? ram_q_a : {8{1'bz}};
|
||||
assign (weak0, weak1) vd = d_cpu_o;
|
||||
assign d_cpu_i = vd;
|
||||
|
||||
|
||||
/* CPU SIGNALS (ideal timings) */
|
||||
// assign n_rd = n_rd_cpu;
|
||||
// assign n_wr = n_wr_cpu;
|
||||
// assign n_iorq = n_iorq_cpu;
|
||||
// assign n_mreq = n_mreq_cpu;
|
||||
// assign n_m1 = n_m1_cpu;
|
||||
// assign n_rfsh = n_rfsh_cpu;
|
||||
// assign a_cpu = a_cpu_cpu;
|
||||
|
||||
/* CPU SIGNALS (Z84C0020 timings) */
|
||||
//assign #400 n_rd = n_rd_cpu; //TdCf(RDf)
|
||||
//assign #400 n_wr = n_wr_cpu; //TdCf(WRf)
|
||||
//assign #400 n_iorq = n_iorq_cpu; //TdCr(IORQf)
|
||||
//assign #400 n_mreq = n_mreq_cpu; //TdCf(MREQf)
|
||||
//assign #450 n_m1 = n_m1_cpu; //TdCr(M1f)
|
||||
//assign #600 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
|
||||
//assign #570 a_cpu = a_cpu_cpu; //TdCr(A)
|
||||
|
||||
/* CPU SIGNALS (Z84C0008 timings) */
|
||||
assign #700 n_rd = n_rd_cpu; //TdCf(RDf)
|
||||
assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
|
||||
assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
|
||||
assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
|
||||
assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
|
||||
assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
|
||||
assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
|
||||
|
||||
/* CPU SIGNALS (Z84C0004 timings) */
|
||||
// assign #850 n_rd = n_rd_cpu; //TdCf(RDf)
|
||||
// assign #800 n_wr = n_wr_cpu; //TdCf(WRf)
|
||||
// assign #750 n_iorq = n_iorq_cpu; //TdCr(IORQf)
|
||||
// assign #850 n_mreq = n_mreq_cpu; //TdCf(MREQf)
|
||||
// assign #1000 n_m1 = n_m1_cpu; //TdCr(M1f)
|
||||
// assign #1300 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
|
||||
// assign #1100 a_cpu = a_cpu_cpu; //TdCr(A)
|
||||
|
||||
/* CLOCKS & RESET */
|
||||
initial begin
|
||||
rst_n = 0;
|
||||
#3000 rst_n = 1;
|
||||
end
|
||||
|
||||
always begin
|
||||
clk28 = 0;
|
||||
#178 clk28 = 1;
|
||||
#179;
|
||||
end
|
||||
|
||||
|
||||
/* TESTBENCH CONTROL */
|
||||
initial begin
|
||||
$dumpfile("testbench_zx_ula.vcd");
|
||||
$dumpvars();
|
||||
#5000000 $finish;
|
||||
// #200000000 $finish;
|
||||
end
|
||||
|
||||
|
||||
always @(clk28) begin
|
||||
// if (v > 100) $dumpoff;
|
||||
// if (~n_iorq) $dumpon;
|
||||
// if (v == 1 && ovf == 1) $finish;
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user