uzix/zx-sizif-xxs
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UzixLS
2021-05-06 12:13:41 +03:00
parent 8f77c02087
commit 11088108f7
66 changed files with 23601 additions and 105 deletions
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8
fpga/rtl/cpucontrol.sv
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@ -20,11 +20,11 @@ module cpucontrol(
input ext_wait_cycle,
input init_done_in,
output n_rstcpu,
output clkcpu,
output reg n_rstcpu,
output reg clkcpu,
output clkcpu_ck,
output clkwait,
output n_int,
output reg n_int,
output n_int_next,
output snow
);
@ -47,7 +47,7 @@ assign snow = (timings != TIMINGS_PENT) && bus.a[14] && ~bus.a[15] && bus.rfsh;
/* CLOCK */
logic [2:0] turbo_wait;
wire turbo_wait_trig0 = bus.rd || bus.wr;
wire turbo_wait_trig1;
reg turbo_wait_trig1;
always @(posedge clk28) begin
turbo_wait_trig1 <= turbo_wait_trig0;
turbo_wait[0] <= turbo == TURBO_14 && turbo_wait_trig0 && !turbo_wait_trig1;

139
fpga/rtl/ps2.v
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@ -12,7 +12,7 @@ module ps2#(
output ps2_dat_out,
input [7:0] zxkb_addr,
output [4:0] zxkb_data,
output reg [4:0] zxkb_data,
output reg key_magic,
output reg key_reset,
output reg key_pause,
@ -56,89 +56,84 @@ always @(posedge clk or negedge rst_n) begin
is_ext <= 0;
key_magic <= 0;
key_pause <= 0;
key2_alt <= 0;
key2_del <= 0;
joy_up <= 0;
joy_down <= 0;
joy_left <= 0;
joy_right <= 0;
joy_fire <= 0;
{joy_up, joy_down, joy_left, joy_right, joy_fire} <= 0;
{key2_a, key2_b, key2_c, key2_d, key2_e, key2_f, key2_g, key2_h, key2_i, key2_j, key2_k, key2_l, key2_m, key2_n} <= 0;
{key2_o, key2_p, key2_q, key2_r, key2_s, key2_t, key2_u, key2_v, key2_w, key2_x, key2_y, key2_z, key2_0, key2_1} <= 0;
{key2_2, key2_3, key2_4, key2_5, key2_6, key2_7, key2_8, key2_9, key2_space, key2_enter, key2_l_shift, key2_r_shift} <= 0;
{key2_l_ctrl, key2_r_ctrl, key2_up, key2_down, key2_left, key2_right, key2_esc, key2_backspace, key2_accent} <= 0;
{key2_minus, key2_equals, key2_back_slash, key2_tab, key2_l_bracket, key2_r_bracket, key2_semicolon, key2_quote} <= 0;
{key2_comma, key2_period, key2_slash, key2_caps, key2_pgup, key2_pgdn} <= 0;
{key2_alt, key2_del} <= 0;
end
else begin
if (rxdone) begin
case ({is_ext, rxbyte})
`PS2_A: key2_a = is_press;
`PS2_B: key2_b = is_press;
`PS2_C: key2_c = is_press;
`PS2_D: key2_d = is_press;
`PS2_E: key2_e = is_press;
`PS2_F: key2_f = is_press;
`PS2_G: key2_g = is_press;
`PS2_H: key2_h = is_press;
`PS2_I: key2_i = is_press;
`PS2_J: key2_j = is_press;
`PS2_K: key2_k = is_press;
`PS2_L: key2_l = is_press;
`PS2_M: key2_m = is_press;
`PS2_N: key2_n = is_press;
`PS2_O: key2_o = is_press;
`PS2_P: key2_p = is_press;
`PS2_Q: key2_q = is_press;
`PS2_R: key2_r = is_press;
`PS2_S: key2_s = is_press;
`PS2_T: key2_t = is_press;
`PS2_U: key2_u = is_press;
`PS2_V: key2_v = is_press;
`PS2_W: key2_w = is_press;
`PS2_X: key2_x = is_press;
`PS2_Y: key2_y = is_press;
`PS2_Z: key2_z = is_press;
`PS2_0: key2_0 = is_press;
`PS2_1: key2_1 = is_press;
`PS2_2: key2_2 = is_press;
`PS2_3: key2_3 = is_press;
`PS2_4: key2_4 = is_press;
`PS2_5: key2_5 = is_press;
`PS2_6: key2_6 = is_press;
`PS2_7: key2_7 = is_press;
`PS2_8: key2_8 = is_press;
`PS2_9: key2_9 = is_press;
`PS2_SPACE: key2_space = is_press;
`PS2_ENTER: key2_enter = is_press;
`PS2_A: key2_a <= is_press;
`PS2_B: key2_b <= is_press;
`PS2_C: key2_c <= is_press;
`PS2_D: key2_d <= is_press;
`PS2_E: key2_e <= is_press;
`PS2_F: key2_f <= is_press;
`PS2_G: key2_g <= is_press;
`PS2_H: key2_h <= is_press;
`PS2_I: key2_i <= is_press;
`PS2_J: key2_j <= is_press;
`PS2_K: key2_k <= is_press;
`PS2_L: key2_l <= is_press;
`PS2_M: key2_m <= is_press;
`PS2_N: key2_n <= is_press;
`PS2_O: key2_o <= is_press;
`PS2_P: key2_p <= is_press;
`PS2_Q: key2_q <= is_press;
`PS2_R: key2_r <= is_press;
`PS2_S: key2_s <= is_press;
`PS2_T: key2_t <= is_press;
`PS2_U: key2_u <= is_press;
`PS2_V: key2_v <= is_press;
`PS2_W: key2_w <= is_press;
`PS2_X: key2_x <= is_press;
`PS2_Y: key2_y <= is_press;
`PS2_Z: key2_z <= is_press;
`PS2_0: key2_0 <= is_press;
`PS2_1: key2_1 <= is_press;
`PS2_2: key2_2 <= is_press;
`PS2_3: key2_3 <= is_press;
`PS2_4: key2_4 <= is_press;
`PS2_5: key2_5 <= is_press;
`PS2_6: key2_6 <= is_press;
`PS2_7: key2_7 <= is_press;
`PS2_8: key2_8 <= is_press;
`PS2_9: key2_9 <= is_press;
`PS2_SPACE: key2_space <= is_press;
`PS2_ENTER: key2_enter <= is_press;
`PS2_L_SHIFT: key2_l_shift = is_press;
`PS2_R_SHIFT: key2_r_shift = is_press;
`PS2_L_CTRL: key2_l_ctrl = is_press;
`PS2_R_CTRL: key2_r_ctrl = is_press;
`PS2_L_SHIFT: key2_l_shift <= is_press;
`PS2_R_SHIFT: key2_r_shift <= is_press;
`PS2_L_CTRL: key2_l_ctrl <= is_press;
`PS2_R_CTRL: key2_r_ctrl <= is_press;
`PS2_UP: key2_up = is_press;
`PS2_DOWN: key2_down = is_press;
`PS2_LEFT: key2_left = is_press;
`PS2_RIGHT: key2_right = is_press;
`PS2_UP: key2_up <= is_press;
`PS2_DOWN: key2_down <= is_press;
`PS2_LEFT: key2_left <= is_press;
`PS2_RIGHT: key2_right <= is_press;
`PS2_ESC: key2_esc = is_press;
`PS2_BACKSPACE: key2_backspace = is_press;
`PS2_ACCENT: key2_accent = is_press;
`PS2_MINUS: key2_minus = is_press;
`PS2_EQUALS: key2_equals = is_press;
`PS2_BACK_SLASH: key2_back_slash = is_press;
`PS2_TAB: key2_tab = is_press;
`PS2_L_BRACKET: key2_l_bracket = is_press;
`PS2_R_BRACKET: key2_r_bracket = is_press;
`PS2_SEMICOLON: key2_semicolon = is_press;
`PS2_QUOTE: key2_quote = is_press;
`PS2_COMMA: key2_comma = is_press;
`PS2_PERIOD: key2_period = is_press;
`PS2_SLASH: key2_slash = is_press;
`PS2_CAPS: key2_caps = is_press;
`PS2_PGUP: key2_pgup = is_press;
`PS2_PGDN: key2_pgdn = is_press;
`PS2_ESC: key2_esc <= is_press;
`PS2_BACKSPACE: key2_backspace <= is_press;
`PS2_ACCENT: key2_accent <= is_press;
`PS2_MINUS: key2_minus <= is_press;
`PS2_EQUALS: key2_equals <= is_press;
`PS2_BACK_SLASH: key2_back_slash <= is_press;
`PS2_TAB: key2_tab <= is_press;
`PS2_L_BRACKET: key2_l_bracket <= is_press;
`PS2_R_BRACKET: key2_r_bracket <= is_press;
`PS2_SEMICOLON: key2_semicolon <= is_press;
`PS2_QUOTE: key2_quote <= is_press;
`PS2_COMMA: key2_comma <= is_press;
`PS2_PERIOD: key2_period <= is_press;
`PS2_SLASH: key2_slash <= is_press;
`PS2_CAPS: key2_caps <= is_press;
`PS2_PGUP: key2_pgup <= is_press;
`PS2_PGDN: key2_pgdn <= is_press;
`PS2_F5: key_magic <= is_press;
`PS2_F11: key_pause <= 1'b0;
@ -211,7 +206,7 @@ wire key_8 = key2_8 | key2_right | key2_l_bracket;
wire key_9 = key2_9 | key2_r_bracket;
wire key_en = key2_enter;
wire key_sp = key2_space | key2_esc;
wire key_cs = key2_l_shift | key2_r_shift | key2_up | key2_down | key2_left | key2_right | key2_esc | key2_backspace |
wire key_cs = key2_l_shift | key2_r_shift | key2_up | key2_down | key2_left | key2_right | key2_esc | key2_backspace
| key2_tab | key2_caps | key2_pgup | key2_pgdn ;
wire key_ss = key2_l_ctrl | key2_r_ctrl | key2_accent | key2_minus | key2_equals | key2_back_slash | key2_l_bracket
| key2_r_bracket | key2_semicolon | key2_quote | key2_comma | key2_period | key2_slash ;

2
fpga/rtl/ps2_rxtx.v
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@ -20,6 +20,7 @@ localparam CLKWAIT_TICKS = int'(CLKWAIT_US*CLK_FREQ/1e6) + 1'b1;
localparam TOUT_US = 100; // must be greater than CLKWAIT_US
localparam TOUT_TICKS = int'(TOUT_US*CLK_FREQ/1e6) + 1'b1;
localparam TIMER_WIDTH = $clog2(TOUT_TICKS);
reg [TIMER_WIDTH-1:0] timer;
reg ps2_freeze; // debounce
@ -43,7 +44,6 @@ always @(posedge clk or negedge rst_n) begin
end
reg [TIMER_WIDTH-1:0] timer;
reg [3:0] bit_cnt;
reg [9:0] rxbits;
assign dataout = rxbits[8:1];

41
fpga/rtl/top.sv
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@ -30,7 +30,7 @@ module zx_ula(
output snd_r,
inout reg ps2_clk,
inout reg ps2_data,
inout reg ps2_dat,
input sd_cd,
input sd_miso_tape_in,
@ -51,6 +51,7 @@ pll pll0(.inclk0(clk_in), .c0(clk40), .c1(clk20), .locked(rst_n));
timings_t timings;
turbo_t turbo;
wire clkwait;
wire screen_read;
reg n_iorq_delayed, a_valid;
always @(posedge clk28) begin
@ -58,18 +59,16 @@ always @(posedge clk28) begin
a_valid <= screen_read == 0;
end
cpu_bus bus();
always @* begin
bus.a = {a[15:13], va[12:0]};
bus.d = vd;
bus.iorq = ~n_iorq;
bus.mreq = ~n_mreq;
bus.m1 = ~n_m1;
bus.rfsh = ~n_rfsh;
bus.rd = ~n_rd;
bus.wr = ~n_wr;
bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0 && a_valid;
bus.a_valid = a_valid;
end
assign bus.a = {a[15:13], va[12:0]};
assign bus.d = vd;
assign bus.iorq = ~n_iorq;
assign bus.mreq = ~n_mreq;
assign bus.m1 = ~n_m1;
assign bus.rfsh = ~n_rfsh;
assign bus.rd = ~n_rd;
assign bus.wr = ~n_wr;
assign bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0 && a_valid;
assign bus.a_valid = a_valid;
/* KEYBOARD */
@ -82,7 +81,7 @@ ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
.rst_n(rst_n),
.clk(clk28),
.ps2_clk_in(ps2_clk),
.ps2_dat_in(ps2_data),
.ps2_dat_in(ps2_dat),
.ps2_clk_out(ps2_clk_out),
.ps2_dat_out(ps2_dat_out),
.zxkb_addr(bus.a[15:8]),
@ -97,7 +96,7 @@ ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
.joy_fire(joy_fire)
);
assign ps2_clk = (ps2_clk_out == 0)? 1'b0 : 1'bz;
assign ps2_data = (ps2_dat_out == 0)? 1'b0 : 1'bz;
assign ps2_dat = (ps2_dat_out == 0)? 1'b0 : 1'bz;
/* SCREEN CONTROLLER */
@ -110,7 +109,7 @@ reg hsync;
reg up_en;
wire [5:0] up_ink_addr, up_paper_addr;
wire [7:0] up_ink, up_paper;
wire screen_read, screen_load, screen_read_up;
wire screen_load, screen_read_up;
wire [14:0] screen_addr;
wire [7:0] attr_next;
wire [8:0] vc, hc;
@ -130,6 +129,7 @@ screen screen0(
.g(g),
.b(b),
.csync(csync),
.vsync(),
.hsync(hsync),
.blink(blink),
@ -173,6 +173,7 @@ assign chroma[2] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
/* CPU CONTROLLER */
reg [2:0] rampage128;
wire div_wait;
wire [7:0] cpucontrol_dout;
wire cpucontrol_dout_active;
@ -249,8 +250,7 @@ wire ports_dout_active;
reg beeper, tape_out;
reg screenpage;
reg rompage128;
reg [2:0] rampage128;
reg [2:0] rampage_ext;
reg [3:0] rampage_ext;
reg [2:0] port_1ffd;
reg port_dffd_d3;
reg port_dffd_d4;
@ -351,6 +351,9 @@ mixer mixer0(
.sd_r0(soundrive_r0),
.sd_r1(soundrive_r1),
.ay_abc(ay_abc),
.ay_mono(ay_mono),
.dac_l(snd_l),
.dac_r(snd_r)
);
@ -443,7 +446,7 @@ rom2ram rom2ram0(
.dataout(rom2ram_dataout)
);
localparam ROM_OFFSET = 24'h00013256;
localparam ROM_OFFSET = 24'h13256;
wire [23:0] asmi_addr = ROM_OFFSET + rom2ram_rom_address;
asmi asmi0(
.clkin(rom2ram_clk),

4
fpga/rtl/turbosound.sv
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@ -66,6 +66,8 @@ YM2149 ym2149_0(
.ctrl_aymode(1'b1),
.port_a_i(8'hff),
.port_b_i(8'hff),
.port_a_o(),
.port_b_o(),
.O_AUDIO_A(ay_a0),
.O_AUDIO_B(ay_b0),
.O_AUDIO_C(ay_c0)
@ -83,6 +85,8 @@ YM2149 ym2149_1(
.ctrl_aymode(1'b1),
.port_a_i(8'hff),
.port_b_i(8'hff),
.port_a_o(),
.port_b_o(),
.O_AUDIO_A(ay_a1),
.O_AUDIO_B(ay_b1),
.O_AUDIO_C(ay_c1)

2
fpga/rtl/ulaplus.sv
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@ -70,7 +70,7 @@ endmodule
module ram(q, a, d, we, clk);
output[7:0] q;
output reg [7:0] q;
input [7:0] d;
input [5:0] a;
input we, clk;