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clocks.sdc: add additional restrictions

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Eugene Lozovoy
2022-10-01 19:37:34 +03:00
parent 7677eb7f80
commit ae202f39a2
1 changed files with 6 additions and 0 deletions
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6
cpld/syn/clocks.sdc
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@ -5,3 +5,9 @@ create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk28}] [
derive_clock_uncertainty
derive_clocks -period 7.2MHz
# One screen read cycle = ~71ns. SRAM speed = 55ns
# So we have about 16ns to setup control signals (n_vwr, va) and read back data (vd)
set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports n_vwr] 13.3ns
set_max_delay -from [get_pins -compatibility_mode screen0|*] -to [get_ports va[*]] 13.3ns
set_max_delay -from [get_ports vd[*]] -to [get_pins -compatibility_mode screen0|*] 2.7ns