add simple testbench

cpld/rtl/top.v

@@ -31,8 +31,8 @@ module sizif512_ext(
     output ym_m,
     output n_ym1_cs,
     output n_ym2_cs,
-    output fm1_ena,
-    output fm2_ena,
+    output reg fm1_ena,
+    output reg fm2_ena,
     output n_saa_cs,
     output saa_clk,
     output midi_clk,
@@ -41,7 +41,7 @@ module sizif512_ext(
     inout [7:0] gd,
     output n_grst,
     output gclk,
-    output n_gint,
+    output reg n_gint,
     input n_grd,
     input n_gwr,
     input n_gm1,