From 2569a40172782b553e56508133e8dc59b27ce50d Mon Sep 17 00:00:00 2001 From: UzixLS Date: Tue, 22 Jun 2021 20:34:27 +0300 Subject: [PATCH] cpld: optimize a bit --- cpld/rtl/top.v | 89 ++++++++++++++++++--------------------------- cpld/syn/clocks.sdc | 4 +- 2 files changed, 38 insertions(+), 55 deletions(-) diff --git a/cpld/rtl/top.v b/cpld/rtl/top.v index 83addfe..e4d381a 100644 --- a/cpld/rtl/top.v +++ b/cpld/rtl/top.v @@ -57,7 +57,6 @@ module sizif512_ext( output gdac3 ); -wire ioreq = n_iorq == 0 && n_m1 == 1'b1; wire ym_ena = cfg[0]; wire saa_ena = cfg[1]; wire gs_ena = cfg[2]; @@ -66,31 +65,28 @@ wire gs_ena = cfg[2]; /* TURBO SOUND FM */ wire port_bffd = a[15:13] == 3'b101 && a[7:0] == 8'hFD && ym_ena; wire port_fffd = a[15:13] == 3'b111 && a[7:0] == 8'hFD && ym_ena; -wire ym_a0 = (~n_rd && port_fffd && ~ym_get_stat) || (~n_wr && port_bffd); reg ym_chip_sel, ym_get_stat; +wire ym_a0 = (~n_rd && port_fffd && ~ym_get_stat) || (~n_wr && port_bffd); +assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq && n_m1); +assign n_ym2_cs = ~( ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq && n_m1); + always @(posedge clkcpu or negedge rst_n) begin if (!rst_n) begin ym_chip_sel <= 0; ym_get_stat <= 0; - n_ym1_cs <= 1'b1; - n_ym2_cs <= 1'b1; fm1_ena <= 0; fm2_ena <= 0; end - else begin - n_ym1_cs <= ~(~ym_chip_sel && (port_bffd || port_fffd) && ioreq); - n_ym2_cs <= ~( ym_chip_sel && (port_bffd || port_fffd) && ioreq); - if (port_fffd && ioreq && ~n_wr && d[7:3] == 5'b11111) begin - ym_chip_sel <= ~d[0]; - ym_get_stat <= ~d[1]; - fm1_ena <= d[2]? 1'b0 : 1'bz; - fm2_ena <= d[2]? 1'b0 : 1'bz; - end + else if (port_fffd && ~n_iorq && ~n_wr && d[7:3] == 5'b11111) begin + ym_chip_sel <= ~d[0]; + ym_get_stat <= ~d[1]; + fm1_ena <= d[2]? 1'b0 : 1'bz; + fm2_ena <= d[2]? 1'b0 : 1'bz; end end reg [5:0] ym_m_cnt = 0; -assign ym_m = ym_m_cnt[5] & ym_ena; +assign ym_m = ym_m_cnt[5]; always @(posedge clk32) begin ym_m_cnt <= ym_m_cnt + 6'd7; end @@ -98,15 +94,7 @@ end /* SAA1099 */ wire port_ff = a[7:0] == 8'hff && saa_ena; -always @(posedge clkcpu or negedge rst_n) begin - if (!rst_n) begin - n_saa_cs <= 1'b1; - end - else begin - n_saa_cs <= ~(ioreq && port_ff && ~n_wr); - end -end - +assign n_saa_cs = ~(port_ff && ~n_iorq && ~n_wr); wire saa_a0 = a[8]; reg [1:0] saa_clk_cnt = 0; @@ -125,10 +113,8 @@ end /* GENERAL SOUND */ -wire g_ioreq = n_giorq == 1'b0 && n_gm1 == 1'b1; - assign gclk = midi_clk; -assign n_grst = rst_n | ~gs_ena; +assign n_grst = rst_n; reg [8:0] g_int_cnt; wire g_int_reload = g_int_cnt[8:6] == 4'b101; @@ -160,9 +146,9 @@ always @(posedge clkcpu or negedge rst_n) begin gs_regbb <= 0; end else begin - if (port_b3 && ioreq && n_wr == 1'b0) + if (port_b3 && ~n_iorq && ~n_wr) gs_regb3 <= d; - if (port_bb && ioreq && n_wr == 1'b0) + if (port_bb && ~n_iorq && ~n_wr) gs_regbb <= d; end end @@ -180,7 +166,7 @@ always @(posedge clk32 or negedge rst_n) begin gs_vol2 <= 0; gs_vol3 <= 0; end - else if (g_ioreq && n_gwr == 1'b0) begin + else if (~n_giorq && ~n_gwr) begin if (ga[3:0] == 4'h0) gs_reg00 <= gd; if (ga[3:0] == 4'h3) gs_reg03 <= gd; if (ga[3:0] == 4'h6) gs_vol0 <= gd[5:0]; @@ -198,7 +184,7 @@ always @(posedge clk32 or negedge rst_n) begin gs_dac2 <= 0; gs_dac3 <= 0; end - else if (n_gmreq == 1'b0 && n_grd == 1'b0 && ga[15:13] == 3'b011) begin + else if (~n_gmreq && ~n_grd && ga[15:13] == 3'b011) begin if (ga[9:8] == 2'b00) gs_dac0 <= gd; if (ga[9:8] == 2'b01) gs_dac1 <= gd; if (ga[9:8] == 2'b10) gs_dac2 <= gd; @@ -211,20 +197,20 @@ reg gs_status0, gs_status7; wire [7:0] gs_status = {gs_status7, 6'b111111, gs_status0}; always @(posedge clk32) begin - if ((g_ioreq && ga[3:0] == 4'h2) || (ioreq && n_rd == 1'b0 && port_b3)) + if ((~n_giorq && n_gm1 && ga[3:0] == 4'h2) || (~n_iorq && ~n_rd && port_b3)) gs_status7 <= 1'b0; - else if ((g_ioreq && ga[3:0] == 4'h3) || (ioreq && n_wr == 1'b0 && port_b3)) + else if ((~n_giorq && n_gm1 && ga[3:0] == 4'h3) || (~n_iorq && ~n_wr && port_b3)) gs_status7 <= 1'b1; - else if (g_ioreq && ga[3:0] == 4'hA) + else if (~n_giorq && n_gm1 && ga[3:0] == 4'hA) gs_status7 <= ~gs_reg00[0]; end always @(posedge clk32) begin - if (g_ioreq && ga[3:0] == 4'h5) + if (~n_giorq && n_gm1 && ga[3:0] == 4'h5) gs_status0 <= 1'b0; - else if (ioreq && n_wr == 1'b0 && port_bb) + else if (~n_iorq && ~n_wr && port_bb) gs_status0 <= 1'b1; - else if (g_ioreq && ga[3:0] == 4'hB) + else if (~n_giorq && n_gm1 && ga[3:0] == 4'hB) gs_status0 <= gs_vol0[5]; end @@ -259,28 +245,25 @@ always @(posedge clk32 or negedge rst_n) begin end /* GS BUS CONTROLLER */ -assign n_grom = (n_gmreq == 0 && ((ga[15:14] == 2'b00) || (ga[15] == 1'b1 && gs_page == 0)))? 1'b0 : 1'b1; -assign n_gram = (n_gmreq == 0 && n_grom == 1'b1)? 1'b0 : 1'b1; +assign n_grom = (~n_gmreq && ((ga[15:14] == 2'b00) || (ga[15] == 1'b1 && gs_page == 0)))? 1'b0 : 1'b1; +assign n_gram = (~n_gmreq && n_grom)? 1'b0 : 1'b1; assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page; assign gd = - (g_ioreq && n_grd == 1'b0 && ga[3:0] == 4'h4)? gs_status : - (g_ioreq && n_grd == 1'b0 && ga[3:0] == 4'h2)? gs_regb3 : - (g_ioreq && n_grd == 1'b0 && ga[3:0] == 4'h1)? gs_regbb : - (n_giorq == 0 && (n_grd == 0 || n_gm1 == 0))? {8{1'b1}} : - {8{1'bz}} ; + (~n_giorq && ~n_grd && ga[3:0] == 4'h4)? gs_status : + (~n_giorq && ~n_grd && ga[3:0] == 4'h2)? gs_regb3 : + (~n_giorq && ~n_grd && ga[3:0] == 4'h1)? gs_regbb : + (~n_giorq && (~n_grd || ~n_gm1))? {8{1'b1}} : + {8{1'bz}} ; /* BUS CONTROLLER */ -assign n_ard = n_rd; -assign n_awr = n_wr; +assign n_ard = n_rd | n_iorq; +assign n_awr = n_wr | n_iorq; -assign aa0 = - (port_bffd || port_fffd)? ym_a0 : - (port_ff)? saa_a0 : - aa0; +assign aa0 = n_iorq? aa0 : a[1]? saa_a0 : ym_a0 ; assign ad = - n_awr == 1'b0 && ioreq && (port_fffd || port_bffd || port_ff)? d : + ~n_awr && ~n_iorq && (port_fffd || port_bffd || port_ff)? d : 8'bzzzzzzzz; @@ -291,9 +274,9 @@ assign n_busrq = 1'bz; assign n_iorqge = (port_fffd || port_bffd || port_b3 || port_bb)? 1'b1 : 1'bz; assign d = - n_rd == 1'b0 && ioreq && (port_fffd || port_bffd)? ad : - n_rd == 1'b0 && ioreq && port_b3? gs_reg03 : - n_rd == 1'b0 && ioreq && port_bb? gs_status : + ~n_rd && ~n_iorq && (port_fffd || port_bffd)? ad : + ~n_rd && ~n_iorq && port_b3? gs_reg03 : + ~n_rd && ~n_iorq && port_bb? gs_status : 8'bzzzzzzzz; diff --git a/cpld/syn/clocks.sdc b/cpld/syn/clocks.sdc index 5dab8d8..1b3670c 100644 --- a/cpld/syn/clocks.sdc +++ b/cpld/syn/clocks.sdc @@ -1,4 +1,4 @@ create_clock -period 32.1MHz -name {clk_32mhz} [get_ports {clk32}] +create_clock -period 14.1MHz -name {clkcpu} [get_ports {clkcpu}] -derive_clock_uncertainty -derive_clocks -period 16.1MHz +create_generated_clock -name {gclk} -divide_by 2 -source [get_ports {clk32}] [get_registers {midi_clk_cnt[2]}]