uzix/zx-sizif-512-ext
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add cpld firmware

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UzixLS
2021-05-25 19:45:59 +03:00
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commit 1211504d1c
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module sizif512_ext(
input rst_n,
input clk32,
input bus0,
input bus1,
input [2:0] cfg,
input clkcpu,
input [15:0] a,
inout [7:0] d,
input n_rd,
input n_wr,
input n_iorq,
input n_mreq,
input n_m1,
input n_rfsh,
input n_int,
input n_nmi,
output n_wait,
output n_busrq,
input n_busack,
input n_halt,
output n_iorqge,
output n_romcsb,
output aa0,
inout [7:0] ad,
output n_ard,
output n_awr,
output ym_m,
output n_ym1_cs,
output n_ym2_cs,
output fm1_ena,
output fm2_ena,
output n_saa_cs,
output saa_clk,
output midi_clk,
input [15:0] ga,
inout [7:0] gd,
output n_grst,
output gclk,
output n_gint,
input n_grd,
input n_gwr,
input n_gm1,
input n_gmreq,
input n_giorq,
output n_grom,
output n_gram,
output [18:15] gma,
output gdac0,
output gdac1,
output gdac2,
output gdac3
);
wire ioreq = n_iorq == 0 && n_m1 == 1'b1;
wire ym_ena = cfg[0];
wire saa_ena = cfg[1];
wire gs_ena = cfg[2];
/* TURBO SOUND FM */
wire port_bffd = a[15:13] == 3'b101 && a[7:0] == 8'hFD && ym_ena;
wire port_fffd = a[15:13] == 3'b111 && a[7:0] == 8'hFD && ym_ena;
wire ym_a0 = (~n_rd && port_fffd && ~ym_get_stat) || (~n_wr && port_bffd);
reg ym_chip_sel, ym_get_stat;
always @(posedge clkcpu or negedge rst_n) begin
if (!rst_n) begin
ym_chip_sel <= 0;
ym_get_stat <= 0;
n_ym1_cs <= 1'b1;
n_ym2_cs <= 1'b1;
fm1_ena <= 0;
fm2_ena <= 0;
end
else begin
n_ym1_cs <= ~(~ym_chip_sel && (port_bffd || port_fffd) && ioreq);
n_ym2_cs <= ~( ym_chip_sel && (port_bffd || port_fffd) && ioreq);
if (port_fffd && ioreq && ~n_wr && d[7:3] == 5'b11111) begin
ym_chip_sel <= ~d[0];
ym_get_stat <= ~d[1];
fm1_ena <= d[2]? 1'b0 : 1'bz;
fm2_ena <= d[2]? 1'b0 : 1'bz;
end
end
end
reg [5:0] ym_m_cnt = 0;
assign ym_m = ym_m_cnt[5] & ym_ena;
always @(posedge clk32) begin
ym_m_cnt <= ym_m_cnt + 6'd7;
end
/* SAA1099 */
wire port_ff = a[7:0] == 8'hff && saa_ena;
always @(posedge clkcpu or negedge rst_n) begin
if (!rst_n) begin
n_saa_cs <= 1'b1;
end
else begin
n_saa_cs <= ~(ioreq && port_ff && ~n_wr);
end
end
wire saa_a0 = a[8];
reg [1:0] saa_clk_cnt = 0;
assign saa_clk = saa_clk_cnt[1] & saa_ena;
always @(posedge clk32) begin
saa_clk_cnt <= saa_clk_cnt + 1'b1;
end
/* MIDI */
reg [2:0] midi_clk_cnt = 0;
assign midi_clk = midi_clk_cnt[2];
always @(posedge clk32) begin
midi_clk_cnt <= midi_clk_cnt + 3'd3;
end
/* GENERAL SOUND */
wire g_ioreq = n_giorq == 1'b0 && n_gm1 == 1'b1;
assign gclk = midi_clk;
assign n_grst = rst_n | ~gs_ena;
reg [8:0] g_int_cnt;
wire g_int_reload = g_int_cnt[8:6] == 4'b101;
always @(posedge gclk or negedge rst_n) begin
if (!rst_n) begin
g_int_cnt <= 0;
n_gint <= 1'b1;
end
else begin
if (g_int_reload)
g_int_cnt <= 0;
else
g_int_cnt <= g_int_cnt + 1'b1;
if (g_int_reload)
n_gint <= 1'b0;
else if (g_int_cnt[5])
n_gint <= 1'b1;
end
end
/* GS EXTERNAL REGISTERS */
reg [7:0] gs_regb3, gs_regbb;
wire port_b3 = a[7:0] == 8'hB3 && gs_ena;
wire port_bb = a[7:0] == 8'hBB && gs_ena;
always @(posedge clkcpu or negedge rst_n) begin
if (!rst_n) begin
gs_regb3 <= 0;
gs_regbb <= 0;
end
else begin
if (port_b3 && ioreq && n_wr == 1'b0)
gs_regb3 <= d;
if (port_bb && ioreq && n_wr == 1'b0)
gs_regbb <= d;
end
end
/* GS INTERNAL REGISTERS */
reg [7:0] gs_reg00, gs_reg03;
wire [3:0] gs_page = gs_reg00[3:0];
reg [5:0] gs_vol0, gs_vol1, gs_vol2, gs_vol3;
always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin
gs_reg00 <= 0;
gs_reg03 <= 0;
gs_vol0 <= 0;
gs_vol1 <= 0;
gs_vol2 <= 0;
gs_vol3 <= 0;
end
else if (g_ioreq && n_gwr == 1'b0) begin
if (ga[3:0] == 4'h0) gs_reg00 <= gd;
if (ga[3:0] == 4'h3) gs_reg03 <= gd;
if (ga[3:0] == 4'h6) gs_vol0 <= gd[5:0];
if (ga[3:0] == 4'h7) gs_vol1 <= gd[5:0];
if (ga[3:0] == 4'h8) gs_vol2 <= gd[5:0];
if (ga[3:0] == 4'h9) gs_vol3 <= gd[5:0];
end
end
reg [7:0] gs_dac0, gs_dac1, gs_dac2, gs_dac3;
always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin
gs_dac0 <= 0;
gs_dac1 <= 0;
gs_dac2 <= 0;
gs_dac3 <= 0;
end
else if (n_gmreq == 1'b0 && n_grd == 1'b0 && ga[15:13] == 3'b011) begin
if (ga[9:8] == 2'b00) gs_dac0 <= gd;
if (ga[9:8] == 2'b01) gs_dac1 <= gd;
if (ga[9:8] == 2'b10) gs_dac2 <= gd;
if (ga[9:8] == 2'b11) gs_dac3 <= gd;
end
end
/* GS STATUS REGISTER */
reg gs_status0, gs_status7;
wire [7:0] gs_status = {gs_status7, 6'b111111, gs_status0};
always @(posedge clk32) begin
if ((g_ioreq && ga[3:0] == 4'h2) || (ioreq && n_rd == 1'b0 && port_b3))
gs_status7 <= 1'b0;
else if ((g_ioreq && ga[3:0] == 4'h3) || (ioreq && n_wr == 1'b0 && port_b3))
gs_status7 <= 1'b1;
else if (g_ioreq && ga[3:0] == 4'hA)
gs_status7 <= ~gs_reg00[0];
end
always @(posedge clk32) begin
if (g_ioreq && ga[3:0] == 4'h5)
gs_status0 <= 1'b0;
else if (ioreq && n_wr == 1'b0 && port_bb)
gs_status0 <= 1'b1;
else if (g_ioreq && ga[3:0] == 4'hB)
gs_status0 <= gs_vol0[5];
end
/* GS DAC */
reg [6:0] dac0v_cnt, dac1v_cnt, dac2v_cnt, dac3v_cnt;
reg [8:0] dac0_cnt, dac1_cnt, dac2_cnt, dac3_cnt;
assign gdac0 = dac0v_cnt[6]? dac0_cnt[8] : 1'b0;
assign gdac1 = dac1v_cnt[6]? dac1_cnt[8] : 1'b0;
assign gdac2 = dac2v_cnt[6]? dac2_cnt[8] : 1'b0;
assign gdac3 = dac3v_cnt[6]? dac3_cnt[8] : 1'b0;
always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin
dac0v_cnt <= 0;
dac1v_cnt <= 0;
dac2v_cnt <= 0;
dac3v_cnt <= 0;
dac0_cnt <= 0;
dac1_cnt <= 0;
dac2_cnt <= 0;
dac3_cnt <= 0;
end
else begin
dac0v_cnt <= dac0v_cnt[5:0] + gs_vol0;
dac1v_cnt <= dac1v_cnt[5:0] + gs_vol1;
dac2v_cnt <= dac2v_cnt[5:0] + gs_vol2;
dac3v_cnt <= dac3v_cnt[5:0] + gs_vol3;
if (dac0v_cnt[6]) dac0_cnt <= dac0_cnt[7:0] + gs_dac0;
if (dac1v_cnt[6]) dac1_cnt <= dac1_cnt[7:0] + gs_dac1;
if (dac2v_cnt[6]) dac2_cnt <= dac2_cnt[7:0] + gs_dac2;
if (dac3v_cnt[6]) dac3_cnt <= dac3_cnt[7:0] + gs_dac3;
end
end
/* GS BUS CONTROLLER */
assign n_grom = (n_gmreq == 0 && ((ga[15:14] == 2'b00) || (ga[15] == 1'b1 && gs_page == 0)))? 1'b0 : 1'b1;
assign n_gram = (n_gmreq == 0 && n_grom == 1'b1)? 1'b0 : 1'b1;
assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page;
assign gd =
(g_ioreq && n_grd == 1'b0 && ga[3:0] == 4'h4)? gs_status :
(g_ioreq && n_grd == 1'b0 && ga[3:0] == 4'h2)? gs_regb3 :
(g_ioreq && n_grd == 1'b0 && ga[3:0] == 4'h1)? gs_regbb :
(n_giorq == 0 && (n_grd == 0 || n_gm1 == 0))? {8{1'b1}} :
{8{1'bz}} ;
/* BUS CONTROLLER */
assign n_ard = n_rd;
assign n_awr = n_wr;
assign aa0 =
(port_bffd || port_fffd)? ym_a0 :
(port_ff)? saa_a0 :
aa0;
assign ad =
n_awr == 1'b0 && ioreq && (port_fffd || port_bffd || port_ff)? d :
8'bzzzzzzzz;
assign n_romcsb = 1'bz;
assign n_wait = 1'bz;
assign n_busrq = 1'bz;
assign n_iorqge = (port_fffd || port_bffd || port_b3 || port_bb)? 1'b1 : 1'bz;
assign d =
n_rd == 1'b0 && ioreq && (port_fffd || port_bffd)? ad :
n_rd == 1'b0 && ioreq && port_b3? gs_reg03 :
n_rd == 1'b0 && ioreq && port_bb? gs_status :
8'bzzzzzzzz;
endmodule

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REVISION = sizif512_ext
.PHONY: build program clean
build:
quartus_sh --no_banner --flow compile sizif512_ext -c ${REVISION}
program:
quartus_pgm --no_banner --mode=jtag -o "BVP;output/${REVISION}.pof"
clean:
rm -rf db incremental_db output
report:
cat output/${REVISION}.*.smsg output/${REVISION}.cmp.rpt |grep -e Error -e Critical -e Warning |grep -v -e "Family doesn't support jitter analysis" -e "Force Fitter to Avoid Periphery Placement Warnings"
export PATH:=/opt/quartus13.0sp1/quartus/bin:/cygdrive/c/Hwdev/quartus130sp1/quartus/bin:${PATH}
-include Makefile.local

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create_clock -period 32.1MHz -name {clk_32mhz} [get_ports {clk32}]
derive_clock_uncertainty
derive_clocks -period 16.1MHz

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cpld/syn/sizif512_ext.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 12:04:27 October 04, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "12:04:27 October 04, 2020"
# Revisions
PROJECT_REVISION = "sizif512_ext"

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cpld/syn/sizif512_ext.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 12:04:27 October 04, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# sizif512_ext_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3256ATC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY sizif512_ext
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:04:27 OCTOBER 04, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE ../rtl/top.v
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_location_assignment PIN_1 -to n_nmi
set_location_assignment PIN_2 -to d[2]
set_location_assignment PIN_5 -to bus1
set_location_assignment PIN_6 -to bus0
set_location_assignment PIN_7 -to ad[1]
set_location_assignment PIN_8 -to ad[2]
set_location_assignment PIN_9 -to ad[3]
set_location_assignment PIN_10 -to ad[4]
set_location_assignment PIN_11 -to ad[5]
set_location_assignment PIN_12 -to ad[6]
set_location_assignment PIN_14 -to ad[7]
set_location_assignment PIN_15 -to n_saa_cs
set_location_assignment PIN_16 -to saa_clk
set_location_assignment PIN_19 -to n_ym2_cs
set_location_assignment PIN_18 -to n_ym1_cs
set_location_assignment PIN_21 -to n_awr
set_location_assignment PIN_22 -to n_ard
set_location_assignment PIN_23 -to aa0
set_location_assignment PIN_25 -to ym_m
set_location_assignment PIN_27 -to ad[0]
set_location_assignment PIN_28 -to fm2_ena
set_location_assignment PIN_29 -to fm1_ena
set_location_assignment PIN_35 -to midi_clk
set_location_assignment PIN_36 -to gdac3
set_location_assignment PIN_37 -to gdac2
set_location_assignment PIN_38 -to gdac1
set_location_assignment PIN_39 -to gdac0
set_location_assignment PIN_40 -to ga[11]
set_location_assignment PIN_41 -to gclk
set_location_assignment PIN_67 -to ga[1]
set_location_assignment PIN_42 -to ga[12]
set_location_assignment PIN_43 -to ga[13]
set_location_assignment PIN_44 -to ga[14]
set_location_assignment PIN_45 -to ga[15]
set_location_assignment PIN_46 -to ga[10]
set_location_assignment PIN_47 -to ga[9]
set_location_assignment PIN_48 -to ga[8]
set_location_assignment PIN_49 -to n_gint
set_location_assignment PIN_53 -to ga[7]
set_location_assignment PIN_54 -to n_gmreq
set_location_assignment PIN_55 -to ga[6]
set_location_assignment PIN_56 -to n_giorq
set_location_assignment PIN_60 -to ga[5]
set_location_assignment PIN_61 -to n_grst
set_location_assignment PIN_62 -to ga[4]
set_location_assignment PIN_63 -to n_gm1
set_location_assignment PIN_65 -to ga[3]
set_location_assignment PIN_66 -to ga[2]
set_location_assignment PIN_68 -to ga[0]
set_location_assignment PIN_69 -to gma[16]
set_location_assignment PIN_70 -to gma[17]
set_location_assignment PIN_71 -to gd[0]
set_location_assignment PIN_72 -to gd[7]
set_location_assignment PIN_74 -to gd[6]
set_location_assignment PIN_75 -to gd[1]
set_location_assignment PIN_78 -to gd[5]
set_location_assignment PIN_79 -to gd[2]
set_location_assignment PIN_80 -to gd[3]
set_location_assignment PIN_81 -to gd[4]
set_location_assignment PIN_82 -to n_grd
set_location_assignment PIN_83 -to n_gram
set_location_assignment PIN_84 -to n_gwr
set_location_assignment PIN_86 -to gma[18]
set_location_assignment PIN_87 -to gma[15]
set_location_assignment PIN_88 -to n_grom
set_location_assignment PIN_90 -to cfg[2]
set_location_assignment PIN_91 -to cfg[1]
set_location_assignment PIN_92 -to cfg[0]
set_location_assignment PIN_93 -to n_busack
set_location_assignment PIN_96 -to n_halt
set_location_assignment PIN_97 -to n_busrq
set_location_assignment PIN_98 -to a[8]
set_location_assignment PIN_99 -to n_wait
set_location_assignment PIN_100 -to a[12]
set_location_assignment PIN_101 -to a[9]
set_location_assignment PIN_102 -to a[11]
set_location_assignment PIN_103 -to a[10]
set_location_assignment PIN_106 -to n_romcsb
set_location_assignment PIN_107 -to n_iorq
set_location_assignment PIN_108 -to d[7]
set_location_assignment PIN_109 -to n_wr
set_location_assignment PIN_110 -to d[6]
set_location_assignment PIN_111 -to n_rd
set_location_assignment PIN_112 -to d[5]
set_location_assignment PIN_113 -to n_iorqge
set_location_assignment PIN_116 -to a[13]
set_location_assignment PIN_117 -to d[4]
set_location_assignment PIN_118 -to d[3]
set_location_assignment PIN_119 -to a[15]
set_location_assignment PIN_120 -to a[14]
set_location_assignment PIN_121 -to n_m1
set_location_assignment PIN_122 -to n_rfsh
set_location_assignment PIN_131 -to n_mreq
set_location_assignment PIN_132 -to a[7]
set_location_assignment PIN_133 -to a[6]
set_location_assignment PIN_134 -to a[4]
set_location_assignment PIN_136 -to a[3]
set_location_assignment PIN_137 -to a[2]
set_location_assignment PIN_138 -to a[1]
set_location_assignment PIN_139 -to a[0]
set_location_assignment PIN_140 -to a[5]
set_location_assignment PIN_141 -to d[0]
set_location_assignment PIN_142 -to d[1]
set_location_assignment PIN_143 -to n_int
set_location_assignment PIN_125 -to clkcpu
set_location_assignment PIN_128 -to clk32
set_location_assignment PIN_127 -to rst_n
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTHESIS_SEED 1
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF