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https://github.com/UzixLS/zx-sizif-128.git
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105b24ffa4
1. quartus 13 may be used for build now; 2. fix small border offset; 3. fix too fast flashing with attribute bit 7.
137 lines
6.3 KiB
Plaintext
Executable File
137 lines
6.3 KiB
Plaintext
Executable File
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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# Date created = 08:15:12 April 28, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# zx_ula_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY MAX7000S
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set_global_assignment -name DEVICE "EPM7128SLC84-15"
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set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
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set_location_assignment PIN_10 -to b
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set_location_assignment PIN_4 -to beeper
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set_location_assignment PIN_83 -to clk14
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set_location_assignment PIN_21 -to clkcpu
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set_location_assignment PIN_5 -to g
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set_location_assignment PIN_18 -to n_int
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set_location_assignment PIN_24 -to n_iorq
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set_location_assignment PIN_22 -to n_m1
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set_location_assignment PIN_25 -to n_mreq
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set_location_assignment PIN_31 -to n_rd
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set_location_assignment PIN_20 -to n_rfsh
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set_location_assignment PIN_30 -to n_romcs
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set_location_assignment PIN_45 -to n_vrd
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set_location_assignment PIN_73 -to n_vwr
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set_location_assignment PIN_29 -to n_wr
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set_location_assignment PIN_8 -to r
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set_location_assignment PIN_1 -to rst_n
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set_location_assignment PIN_81 -to tape_out
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set_location_assignment PIN_48 -to va[16]
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set_location_assignment PIN_64 -to va[15]
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set_location_assignment PIN_61 -to va[14]
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set_location_assignment PIN_67 -to va[13]
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set_location_assignment PIN_69 -to va[12]
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set_location_assignment PIN_70 -to va[11]
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set_location_assignment PIN_75 -to va[10]
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set_location_assignment PIN_76 -to va[9]
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set_location_assignment PIN_74 -to va[8]
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set_location_assignment PIN_65 -to va[7]
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set_location_assignment PIN_77 -to va[6]
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set_location_assignment PIN_46 -to va[5]
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set_location_assignment PIN_44 -to va[4]
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set_location_assignment PIN_63 -to va[3]
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set_location_assignment PIN_68 -to va[2]
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set_location_assignment PIN_60 -to va[1]
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set_location_assignment PIN_58 -to va[0]
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set_location_assignment PIN_51 -to vd[7]
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set_location_assignment PIN_55 -to vd[6]
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set_location_assignment PIN_54 -to vd[5]
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set_location_assignment PIN_57 -to vd[4]
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set_location_assignment PIN_56 -to vd[3]
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set_location_assignment PIN_52 -to vd[2]
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set_location_assignment PIN_49 -to vd[1]
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set_location_assignment PIN_50 -to vd[0]
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
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set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
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set_location_assignment PIN_6 -to i
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set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
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set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
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set_location_assignment PIN_28 -to a0
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set_location_assignment PIN_27 -to a1
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set_location_assignment PIN_17 -to a14
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set_location_assignment PIN_16 -to a15
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set_global_assignment -name AUTO_RESOURCE_SHARING OFF
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set_global_assignment -name AUTO_LCELL_INSERTION OFF
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set_location_assignment PIN_9 -to csync
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set_location_assignment PIN_2 -to clk16
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set_location_assignment PIN_11 -to chroma[1]
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set_location_assignment PIN_12 -to chroma[0]
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set_location_assignment PIN_33 -to kd[1]
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set_location_assignment PIN_34 -to kd[0]
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set_location_assignment PIN_35 -to kd[3]
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set_location_assignment PIN_36 -to kd[2]
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set_location_assignment PIN_37 -to kd[4]
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set_location_assignment PIN_39 -to ay_bc1
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set_location_assignment PIN_40 -to ay_bdir
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set_location_assignment PIN_41 -to ay_clk
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set_location_assignment PIN_79 -to tape_in
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set_location_assignment PIN_80 -to ra14
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set_global_assignment -name FMAX_REQUIREMENT "16 MHz" -section_id clk16
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set_instance_assignment -name CLOCK_SETTINGS clk16 -to clk16
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set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu
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set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name AUTO_TURBO_BIT ON
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set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
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set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
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set_global_assignment -name SLOW_SLEW_RATE OFF
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name VHDL_FILE chroma_gen16.vhd
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set_global_assignment -name VERILOG_FILE top.v
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set_global_assignment -name VERILOG_INCLUDE_FILE util.vh |