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51 lines
715 B
Verilog
51 lines
715 B
Verilog
`define USE_FPGA
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`include "../cpld/top.v"
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`timescale 100ps/10ps
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module testbench_zx_ula();
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reg rst_n;
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reg clk14;
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/* ULA */
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zx_ula zx_ula1(
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.rst_n(rst_n),
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.clk14(clk14)
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);
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/* CLOCKS & RESET */
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initial begin
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rst_n = 0;
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#3000 rst_n = 1;
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end
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always begin
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clk14 = 0;
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#357 clk14 = 1;
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#358;
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end
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initial zx_ula1.hc0 = 0;
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initial zx_ula1.vc = 0;
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/* TESTBENCH CONTROL */
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initial begin
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$dumpfile("testbench_zx_ula.vcd");
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$dumpvars();
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#5000000 $finish;
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//#21000000 $finish;
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end
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always @(clk14) begin
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// if (v > 100) $dumpoff;
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// if (~n_iorq) $dumpon;
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// if (v == 1 && ovf == 1) $finish;
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end
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endmodule
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