# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2009 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II # Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition # Date created = 08:15:12 April 28, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # zx_ula_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY MAX7000S set_global_assignment -name DEVICE "EPM7128SLC84-15" set_global_assignment -name TOP_LEVEL_ENTITY zx_ula set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL set_location_assignment PIN_10 -to b set_location_assignment PIN_4 -to beeper set_location_assignment PIN_83 -to clk14 set_location_assignment PIN_21 -to clkcpu set_location_assignment PIN_5 -to g set_location_assignment PIN_18 -to n_int set_location_assignment PIN_24 -to n_iorq set_location_assignment PIN_22 -to n_m1 set_location_assignment PIN_25 -to n_mreq set_location_assignment PIN_31 -to n_rd set_location_assignment PIN_20 -to n_rfsh set_location_assignment PIN_30 -to n_romcs set_location_assignment PIN_45 -to n_vrd set_location_assignment PIN_73 -to n_vwr set_location_assignment PIN_29 -to n_wr set_location_assignment PIN_8 -to r set_location_assignment PIN_1 -to rst_n set_location_assignment PIN_81 -to tape_out set_location_assignment PIN_48 -to va[16] set_location_assignment PIN_64 -to va[15] set_location_assignment PIN_61 -to va[14] set_location_assignment PIN_67 -to va[13] set_location_assignment PIN_69 -to va[12] set_location_assignment PIN_70 -to va[11] set_location_assignment PIN_75 -to va[10] set_location_assignment PIN_76 -to va[9] set_location_assignment PIN_74 -to va[8] set_location_assignment PIN_65 -to va[7] set_location_assignment PIN_77 -to va[6] set_location_assignment PIN_46 -to va[5] set_location_assignment PIN_44 -to va[4] set_location_assignment PIN_63 -to va[3] set_location_assignment PIN_68 -to va[2] set_location_assignment PIN_60 -to va[1] set_location_assignment PIN_58 -to va[0] set_location_assignment PIN_51 -to vd[7] set_location_assignment PIN_55 -to vd[6] set_location_assignment PIN_54 -to vd[5] set_location_assignment PIN_57 -to vd[4] set_location_assignment PIN_56 -to vd[3] set_location_assignment PIN_52 -to vd[2] set_location_assignment PIN_49 -to vd[1] set_location_assignment PIN_50 -to vd[0] set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED set_global_assignment -name FMAX_REQUIREMENT "14 MHz" set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14 set_location_assignment PIN_6 -to i set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14 set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu set_location_assignment PIN_28 -to a0 set_location_assignment PIN_27 -to a1 set_location_assignment PIN_17 -to a14 set_location_assignment PIN_16 -to a15 set_global_assignment -name AUTO_RESOURCE_SHARING OFF set_global_assignment -name AUTO_LCELL_INSERTION OFF set_location_assignment PIN_9 -to csync set_location_assignment PIN_2 -to clkpal set_location_assignment PIN_11 -to chroma[1] set_location_assignment PIN_12 -to chroma[0] set_location_assignment PIN_33 -to kd[1] set_location_assignment PIN_34 -to kd[0] set_location_assignment PIN_35 -to kd[3] set_location_assignment PIN_36 -to kd[2] set_location_assignment PIN_37 -to kd[4] set_location_assignment PIN_39 -to ay_bc1 set_location_assignment PIN_40 -to ay_bdir set_location_assignment PIN_41 -to ay_clk set_location_assignment PIN_79 -to tape_in set_location_assignment PIN_80 -to ra14 set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name AUTO_TURBO_BIT ON set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING NORMAL set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF set_global_assignment -name SLOW_SLEW_RATE OFF set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF set_global_assignment -name SDC_FILE clocks.sdc set_global_assignment -name VERILOG_FILE chroma_gen.v set_global_assignment -name VERILOG_FILE top.v