uzix/zx-sizif-128
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cleanup quartus project files

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UzixLS
2020-04-19 11:30:11 +03:00
parent dff7f28b0e
commit bacedc947f
3 changed files with 7 additions and 22 deletions
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5
.gitignore vendored
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@ -1,9 +1,10 @@
db/
incremental_db/
output/
*.dpf
*.cdf
*.qws
*.bak
*.*~
top-old.v
*.dpf
*.qws
sizif*.rom

13
zx_ula.cdf
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@ -1,13 +0,0 @@
/* Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM7128SL84) Path("//VBOXSVR/Desktop/zx-sizif-128/") File("zx_ula.pof") MfrSpec(OpMask(3));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

9
zx_ula.qsf
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@ -90,7 +90,6 @@ set_location_assignment PIN_56 -to vd[3]
set_location_assignment PIN_52 -to vd[2]
set_location_assignment PIN_49 -to vd[1]
set_location_assignment PIN_50 -to vd[0]
set_global_assignment -name MISC_FILE "E:/ws/quartus/zx_ula/zx_ula.dpf"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
@ -106,9 +105,6 @@ set_location_assignment PIN_16 -to a15
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_location_assignment PIN_9 -to csync
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh
set_global_assignment -name VHDL_FILE chroma_gen16.vhd
set_location_assignment PIN_2 -to clk16
set_location_assignment PIN_11 -to chroma[1]
set_location_assignment PIN_12 -to chroma[0]
@ -117,7 +113,6 @@ set_location_assignment PIN_34 -to kd[0]
set_location_assignment PIN_35 -to kd[3]
set_location_assignment PIN_36 -to kd[2]
set_location_assignment PIN_37 -to kd[4]
set_global_assignment -name MISC_FILE "E:/ws/quartus/zx-sizif-128/zx_ula.dpf"
set_location_assignment PIN_39 -to ay_bc1
set_location_assignment PIN_40 -to ay_bdir
set_location_assignment PIN_41 -to ay_clk
@ -132,7 +127,9 @@ set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name MISC_FILE "Z:/zx-sizif-128/zx_ula.dpf"
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name VHDL_FILE chroma_gen16.vhd
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh