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UzixLS
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168
cpld/chroma_gen16.vhd Executable file
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--------------------------------------------------------------------------------
-- Company:
-- Engineer: Joerg Wolfram
--
-- Create Date: 04.03.2007
-- Design Name:
-- Module Name: chroma generator
-- Project Name: fbas-encoder
-- Target Device:
-- Tool versions:
-- Description: generates the chroma component of the signal
--
-- Revision: 0.31
-- License: GPL
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity chroma_gen is
port (
-------------------------------------------------------------------------------
--- io
-------------------------------------------------------------------------------
cg_clock: in std_logic; --- input clock
cg_enable: in std_logic; --- colour enable
cg_hsync: in std_logic; --- hor. sync
cg_pnsel: in std_logic; --- system (pal/ntsc)
cg_rgb: in std_logic_vector(2 downto 0); --- rgb input
cg_out: out std_logic_vector(2 downto 0)); --- chroma out
end entity chroma_gen;
---############################################################################
--- 16MHz
---############################################################################
architecture clock16 of chroma_gen is
signal carrier: std_logic_vector(14 downto 0);
signal bcounter: std_logic_vector(3 downto 0);
signal phase: std_logic_vector(3 downto 0);
signal scarrier: std_logic_vector(3 downto 0);
signal oddeven: std_logic;
signal burst,bstop: std_logic;
signal cenable: std_logic;
begin
-------------------------------------------------------------------------------
--- DDS for PAL-carrier
-------------------------------------------------------------------------------
process (cg_clock) is
begin
if (rising_edge(cg_clock)) then
if (cg_pnsel='0') then
carrier <= carrier + 9080;
else
carrier <= carrier + 7331;
end if;
end if;
end process;
-------------------------------------------------------------------------------
--- burst generator
-------------------------------------------------------------------------------
process (bcounter) is
begin
if (bcounter="0000") then
bstop <= '1';
else
bstop <= '0';
end if;
end process;
process (cg_hsync,bstop,carrier(14)) is
begin
if (cg_hsync='0') then
bcounter <= "0100";
elsif ((rising_edge(carrier(14))) and (bstop='0')) then
bcounter <= bcounter + 1;
end if;
end process;
burst <= bcounter(3);
-------------------------------------------------------------------------------
--- odd/even line
-------------------------------------------------------------------------------
process (cg_hsync,cg_pnsel) is
begin
if (rising_edge(cg_hsync)) then
if (cg_pnsel='0') then
oddeven <= not(oddeven);
else
oddeven <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
--- carrier phase
-------------------------------------------------------------------------------
process (cg_rgb,burst,oddeven) is
begin
if (burst='1') then
if ((oddeven = '0') and (cg_pnsel='0')) then
phase <= "0110"; --- burst phase 135 deg
else
phase <= "1010"; --- burst phase -135 deg
end if;
else
if (oddeven = '0') then
case (cg_rgb) is
when "001" => phase <= "0000"; --- blue phase
when "010" => phase <= "0101"; --- red phase
when "011" => phase <= "0011"; --- magenta phase
when "100" => phase <= "1011"; --- green phase
when "101" => phase <= "1101"; --- cyan phase
when "110" => phase <= "0111"; --- yellow phase
when others => phase <= "0000"; --- dummy function
end case;
else
case (cg_rgb) is
when "001" => phase <= "0000"; --- blue phase
when "010" => phase <= "1011"; --- red phase
when "011" => phase <= "1101"; --- magenta phase
when "100" => phase <= "0101"; --- green phase
when "101" => phase <= "0011"; --- cyan phase
when "110" => phase <= "1001"; --- yellow phase
when others => phase <= "0000"; --- dummy function
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------
--- modulated carrier
-------------------------------------------------------------------------------
scarrier <= carrier(14 downto 11) + phase;
-------------------------------------------------------------------------------
--- colour enable
-------------------------------------------------------------------------------
process (cg_rgb,cg_enable) is
begin
if ((cg_rgb/="000") and (cg_rgb/="111") and (cg_enable='1')) then
cenable <= '1';
else
cenable <= '0';
end if;
end process;
-------------------------------------------------------------------------------
--- chroma signal
-------------------------------------------------------------------------------
process (cg_clock) is
begin
if (rising_edge(cg_clock)) then
cg_out(2) <= cenable;
cg_out(1) <= burst;
cg_out(0) <= scarrier(3);
end if;
end process;
end architecture clock16;

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cpld/top.v Executable file
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`include "util.vh"
module zx_ula(
input rst_n,
input clk14,
input clk16,
output clkcpu,
inout [7:0] vd,
inout [16:0] va,
output ra14,
input a0,
input a1,
input a14,
input a15,
input n_rd,
input n_wr,
input n_mreq,
input n_iorq,
input n_m1,
input n_rfsh,
output reg n_int,
output n_vrd,
output n_vwr,
output reg n_romcs,
input [4:0] kd,
input tape_in,
output tape_out,
output beeper,
output ay_clk,
output reg ay_bdir,
output reg ay_bc1,
output reg r,
output reg g,
output reg b,
output reg i,
output [1:0] chroma,
output reg csync
);
wire timings = 0;
wire turbo = 0;
wire [2:0] border;
reg n_iorq_delayed;
always @(posedge clkcpu)
n_iorq_delayed <= n_iorq;
wire n_iorq0 = n_iorq | n_iorq_delayed;
/* SCREEN CONTROLLER */
localparam H_AREA = 256;
localparam V_AREA = 192;
localparam SCREEN_DELAY = 8;
localparam H_LBORDER_S48 = 32 - SCREEN_DELAY;
localparam H_RBORDER_S48 = 64 + SCREEN_DELAY;
localparam H_BLANK1_S48 = 16;
localparam H_SYNC_S48 = 32;
localparam H_BLANK2_S48 = 48;
localparam H_TOTAL_S48 = H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48 + H_BLANK2_S48 + H_LBORDER_S48;
localparam V_BBORDER_S48 = 56;
localparam V_SYNC_S48 = 8;
localparam V_TBORDER_S48 = 56;
localparam V_TOTAL_S48 = V_AREA + V_BBORDER_S48 + V_SYNC_S48 + V_TBORDER_S48;
localparam H_LBORDER_S128 = 48 - SCREEN_DELAY;
localparam H_RBORDER_S128 = 48 + SCREEN_DELAY;
localparam H_BLANK1_S128 = 28;
localparam H_SYNC_S128 = 32;
localparam H_BLANK2_S128 = 44;
localparam H_TOTAL_S128 = H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128 + H_LBORDER_S128;
localparam V_BBORDER_S128 = 56;
localparam V_SYNC_S128 = 8;
localparam V_TBORDER_S128 = 55;
localparam V_TOTAL_S128 = V_AREA + V_BBORDER_S128 + V_SYNC_S128 + V_TBORDER_S128;
localparam H_LBORDER_PENT = 64 - SCREEN_DELAY;
localparam H_RBORDER_PENT = 64 + SCREEN_DELAY;
localparam H_BLANK1_PENT = 0;
localparam H_SYNC_PENT = 32;
localparam H_BLANK2_PENT = 32;
localparam H_TOTAL_PENT = H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT + H_BLANK2_PENT + H_LBORDER_PENT;
localparam V_BBORDER_PENT = 56;
localparam V_SYNC_PENT = 8;
localparam V_TBORDER_PENT = 64;
localparam V_TOTAL_PENT = V_AREA + V_BBORDER_PENT + V_SYNC_PENT + V_TBORDER_PENT;
reg [`CLOG2(`MAX(V_TOTAL_S128, V_TOTAL_PENT))-1:0] vc;
reg [`CLOG2(`MAX(H_TOTAL_S128, H_TOTAL_PENT)):0] hc0;
wire [`CLOG2(`MAX(H_TOTAL_S128, H_TOTAL_PENT))-1:0] hc = hc0[$bits(hc0)-1:1];
wire hc0_reset = timings?
hc0 == (H_TOTAL_S128<<1) - 1'b1 :
hc0 == (H_TOTAL_PENT<<1) - 1'b1 ;
wire vc_reset = timings?
vc == V_TOTAL_S128 - 1'b1 :
vc == V_TOTAL_PENT - 1'b1 ;
wire hsync0 = timings?
(hc >= (H_AREA + H_RBORDER_S128 + H_BLANK1_S128)) &&
(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128)) :
(hc[8:5] == 4'b1010);
wire vsync0 = timings?
(vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128)) :
(vc[7:3] == 5'b11111) ;
wire blank = timings?
((vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128))) ||
((hc >= (H_AREA + H_RBORDER_S128)) &&
(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128))) :
((vc[7:3] == 5'b11111) ||
(hc[8:6] == 3'b101));
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
hc0 <= 0;
vc <= 0;
end
else if (hc0_reset) begin
hc0 <= 0;
if (vc_reset) begin
vc <= 0;
end
else begin
vc <= vc + 1'b1;
end
end
else begin
hc0 <= hc0 + 1'b1;
end
end
reg [3:0] blink_cnt;
wire blink = blink_cnt[$bits(blink_cnt)-1];
always @(posedge n_int or negedge rst_n) begin
if (!rst_n)
blink_cnt <= 0;
else
blink_cnt <= blink_cnt + 1'b1;
end
reg [7:0] bitmap, attr, bitmap_next, attr_next;
wire pixel = bitmap[7];
always @(posedge clk14) begin
if (hc0[0]) begin
if (blank)
{i, g, r, b} = 4'b0000;
else begin
{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
i = (g | r | b) & attr[6];
end
csync <= ~(vsync0 ^ hsync0);
end
end
reg screen_read;
wire attr_read = screen_read & ~hc0[0];
wire bitmap_read = screen_read & hc0[0];
wire [14:0] bitmap_addr = { 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] };
wire [14:0] attr_addr = { 5'b10110, vc[7:3], hc[7:3] };
wire [14:0] screen_addr = attr_read? attr_addr : bitmap_addr;
wire screen_load = (vc < V_AREA) && (hc < H_AREA);
wire screen_show = (vc < V_AREA) && (hc >= SCREEN_DELAY) && (hc < H_AREA + SCREEN_DELAY);
wire screen_update = hc0[3:0] == 4'b1111;
wire border_update = ((screen_load == 0 && screen_show == 0) || (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0 && timings == 0))
&& (timings == 0 || hc0[3:0] == 4'b1111);
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
screen_read <= 0;
attr <= 0;
bitmap <= 0;
attr_next <= 0;
bitmap_next <= 0;
end
else begin
screen_read <= screen_load && (n_mreq == 1 && n_iorq == 1);
if (attr_read)
attr_next <= vd;
if (bitmap_read)
bitmap_next <= vd;
if (screen_load && screen_update)
attr <= attr_next;
else if (border_update)
attr <= {2'b00, border, 3'b000};
if (screen_load && screen_update)
bitmap <= bitmap_next;
else if (hc0[0])
bitmap <= {bitmap[6:0], 1'b0};
end
end
wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
/* PORT #FE */
wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
reg port_fe_rd;
always @(posedge clk14)
port_fe_rd <= port_fe_cs && n_rd == 0;
wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
reg [7:0] port_fe;
assign beeper = port_fe[4];
assign tape_out = port_fe[3] ^ tape_in;
assign border = port_fe[2:0];
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n)
port_fe <= 0;
else if (port_fe_cs && n_wr == 0)
port_fe <= vd;
end
/* PORT #7FFD */
wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0;
reg [7:0] port_7ffd;
wire [2:0] rambank = port_7ffd[2:0];
wire vbank = port_7ffd[3];
wire rombank = port_7ffd[4];
wire lock_7ffd = port_7ffd[5];
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n)
port_7ffd <= 0;
else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0)
port_7ffd <= vd;
end
/* INT GENERATOR */
localparam INT_V_S48 = 248;
localparam INT_H_FROM_S48 = 0;
localparam INT_H_TO_S48 = 63;
localparam INT_V_S128 = 248;
localparam INT_H_FROM_S128 = 2;
localparam INT_H_TO_S128 = 65;
localparam INT_V_PENT = 239;
localparam INT_H_FROM_PENT = 320;
localparam INT_H_TO_PENT = 384;
always @(posedge clk14) begin
n_int <= timings?
(vc != INT_V_S128 || hc < INT_H_FROM_S128 || hc > INT_H_TO_S128) :
(vc != INT_V_PENT || hc < INT_H_FROM_PENT || hc > INT_H_TO_PENT) ;
end
/* CLOCK */
reg [2:0] clk_cnt;
always @(posedge clk14) begin
clk_cnt <= clk_cnt + 1'b1;
end
assign clkcpu = turbo? clk_cnt[0] : clk_cnt[1];
/* AY */
always @(posedge clkcpu or negedge rst_n) begin
if (!rst_n) begin
ay_bc1 <= 0;
ay_bdir <= 0;
end
else begin
ay_bc1 <= xa[15] == 1 && xa[14] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0;
ay_bdir <= xa[15] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0 && n_wr == 0;
end
end
assign ay_clk = clk_cnt[2];
/* VIDEO */
reg [2:0] chroma0;
chroma_gen chroma_gen1(
.cg_clock(clk16),
.cg_rgb({g,r,b}),
.cg_hsync(~hsync0),
.cg_enable(1'b1),
.cg_pnsel(1'b0),
.cg_out(chroma0)
);
assign chroma[0] = chroma0[1]? chroma0[0] : 1'bz;
assign chroma[1] = chroma0[2]? chroma0[0] : 1'bz;
/* MEMORY CONTROLLER */
// 7ffe a15-14 va16-14
// xxx 01 010 bank 2
// xxx 10 101 bank 5
// 000 11 000 bank 0
// 001 11 001 bank 1 | contended
// 010 11 010 bank 2
// 011 11 011 bank 3 | contended
// 100 11 100 bank 4
// 101 11 101 bank 5 | contended (video)
// 110 11 110 bank 6
// 111 11 111 bank 7 | contended (video alt)
// 7ffe a15-14 ra14
// 0 00 0 rom0
// 1 00 1 rom1
wire n_vcs_cpu = n_mreq | ~(a15 | a14);
assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1 ;
assign n_vwr = ((n_vcs_cpu == 0 && n_wr == 0) && screen_read == 0)? 1'b0 : 1'b1;
always @(posedge clkcpu) begin
n_romcs <= n_mreq | a15 | a14;
end
assign ra14 = rombank;
assign va[16:0] =
screen_read? {1'b1, vbank, screen_addr} :
a15 & a14? {rambank, {14{1'bz}}} :
{a14, a15, a14, {14{1'bz}}};
assign vd[7:0] =
port_fe_rd? port_fe_data :
n_iorq0 == 0 && (n_rd == 0 | n_m1 == 0)? {8{1'b1}} :
{8{1'bz}};
endmodule

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`define MAX(a,b) (a)>(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define TZER(N) (!`ISDEF(N) || (N) <= 0) ? 'hx : \
(~|((N)&'h7fff_ffff)?31:(~|((N)&'h3fff_ffff)?30: \
(~|((N)&'h1fff_ffff)?29:(~|((N)&'hfff_ffff)?28: \
(~|((N)&'h7ff_ffff)?27:(~|((N)&'h3ff_ffff)?26:(~|((N)&'h1ff_ffff)?25:(~|((N)&'hff_ffff)?24: \
(~|((N)&'h7f_ffff)?23:(~|((N)&'h3f_ffff)?22:(~|((N)&'h1f_ffff)?21:(~|((N)&'hf_ffff)?20: \
(~|((N)&'h7_ffff)?19:(~|((N)&'h3_ffff)?18:(~|((N)&'h1_ffff)?17:(~|((N)&'hffff)?16: \
(~|((N)&'h7fff)?15:(~|((N)&'h3fff)?14:(~|((N)&'h1fff)?13:(~|((N)&'hfff)?12: \
(~|((N)&'h7ff)?11:(~|((N)&'h3ff)?10:(~|((N)&'h1ff)?9:(~|((N)&'hff)?8: \
(~|((N)&'h7f)?7:(~|((N)&'h3f)?6:(~|((N)&'h1f)?5:(~|((N)&'hf)?4: \
(~|((N)&'h7)?3:(~|((N)&'h3)?2: \
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
`define CLOG2_CORE(N) \
((N)&'h8000_0000 ?32:((N)&'h4000_0000 ?31:((N)&'h2000_0000 ?30:((N)&'h1000_0000 ?29: \
((N)&'h800_0000 ?28:((N)&'h400_0000 ?27:((N)&'h200_0000 ?26:((N)&'h100_0000 ?25: \
((N)&'h80_0000 ?24:((N)&'h40_0000 ?23:((N)&'h20_0000 ?22:((N)&'h10_0000 ?21: \
((N)&'h8_0000 ?20:((N)&'h4_0000 ?19:((N)&'h2_0000 ?18:((N)&'h1_0000 ?17: \
((N)&'h8000 ?16:((N)&'h4000 ?15:((N)&'h2000 ?14:((N)&'h1000 ?13: \
((N)&'h800 ?12:((N)&'h400 ?11:((N)&'h200 ?10:((N)&'h100 ?9: \
((N)&'h80 ?8:((N)&'h40 ?7:((N)&'h20 ?6:((N)&'h10 ?5: \
((N)&'h8 ?4:((N)&'h4 ?3:((N)&'h2 ?2: \
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define CLOG2(N) ((!`ISDEF(N) || (N) <= 0) ? 'hx : `CLOG2_CORE((N)-1)) //"Ceil(LOG2(N))"
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDCN(N) (`ISDEF(N) && ((N) == 0 || (N) == 1) ? 1 : `CLOG2(N)) //"WIDth Computation from N"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
`define URAND(MIN, MAX) ((MAX) < (MIN) ? 1'bx : (((MAX) == (MIN)) ? (MIN) : \
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define ISHEXD(L) (`ISDEF(L) && ((L) >= "A" && (L) <= "F" || (L) >= "a" && (L) <= "f" || \
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
`define ISHEXDX(L) (`ISHEXD(L) || \
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define HEXD2DEC(L) (!`ISHEXD(L) ? \
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
//HEXadecimal Digit to decimal number, on all incorrect inputs returns 0.

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"

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cpld/zx_ula.qsf Executable file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_10 -to b
set_location_assignment PIN_4 -to beeper
set_location_assignment PIN_83 -to clk14
set_location_assignment PIN_21 -to clkcpu
set_location_assignment PIN_5 -to g
set_location_assignment PIN_18 -to n_int
set_location_assignment PIN_24 -to n_iorq
set_location_assignment PIN_22 -to n_m1
set_location_assignment PIN_25 -to n_mreq
set_location_assignment PIN_31 -to n_rd
set_location_assignment PIN_20 -to n_rfsh
set_location_assignment PIN_30 -to n_romcs
set_location_assignment PIN_45 -to n_vrd
set_location_assignment PIN_73 -to n_vwr
set_location_assignment PIN_29 -to n_wr
set_location_assignment PIN_8 -to r
set_location_assignment PIN_1 -to rst_n
set_location_assignment PIN_81 -to tape_out
set_location_assignment PIN_48 -to va[16]
set_location_assignment PIN_64 -to va[15]
set_location_assignment PIN_61 -to va[14]
set_location_assignment PIN_67 -to va[13]
set_location_assignment PIN_69 -to va[12]
set_location_assignment PIN_70 -to va[11]
set_location_assignment PIN_75 -to va[10]
set_location_assignment PIN_76 -to va[9]
set_location_assignment PIN_74 -to va[8]
set_location_assignment PIN_65 -to va[7]
set_location_assignment PIN_77 -to va[6]
set_location_assignment PIN_46 -to va[5]
set_location_assignment PIN_44 -to va[4]
set_location_assignment PIN_63 -to va[3]
set_location_assignment PIN_68 -to va[2]
set_location_assignment PIN_60 -to va[1]
set_location_assignment PIN_58 -to va[0]
set_location_assignment PIN_51 -to vd[7]
set_location_assignment PIN_55 -to vd[6]
set_location_assignment PIN_54 -to vd[5]
set_location_assignment PIN_57 -to vd[4]
set_location_assignment PIN_56 -to vd[3]
set_location_assignment PIN_52 -to vd[2]
set_location_assignment PIN_49 -to vd[1]
set_location_assignment PIN_50 -to vd[0]
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
set_location_assignment PIN_6 -to i
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_location_assignment PIN_28 -to a0
set_location_assignment PIN_27 -to a1
set_location_assignment PIN_17 -to a14
set_location_assignment PIN_16 -to a15
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_location_assignment PIN_9 -to csync
set_location_assignment PIN_2 -to clk16
set_location_assignment PIN_11 -to chroma[1]
set_location_assignment PIN_12 -to chroma[0]
set_location_assignment PIN_33 -to kd[1]
set_location_assignment PIN_34 -to kd[0]
set_location_assignment PIN_35 -to kd[3]
set_location_assignment PIN_36 -to kd[2]
set_location_assignment PIN_37 -to kd[4]
set_location_assignment PIN_39 -to ay_bc1
set_location_assignment PIN_40 -to ay_bdir
set_location_assignment PIN_41 -to ay_clk
set_location_assignment PIN_79 -to tape_in
set_location_assignment PIN_80 -to ra14
set_global_assignment -name FMAX_REQUIREMENT "16 MHz" -section_id clk16
set_instance_assignment -name CLOCK_SETTINGS clk16 -to clk16
set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name VHDL_FILE chroma_gen16.vhd
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh