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rewrite chroma_gen in verilog

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UzixLS
2020-10-08 22:44:40 +03:00
parent 7d4d9fd525
commit 6369747d58
5 changed files with 140 additions and 171 deletions
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137
cpld/chroma_gen.v Normal file
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@ -0,0 +1,137 @@
// Based on Joerg Wolfram's code //
module chroma_gen #(
parameter CLK_FREQ
) (
input cg_clock, // input clock
input cg_enable, // colour enable
input cg_hsync, // hor. sync
input cg_pnsel, // system (pal/ntsc)
input [2:0] cg_rgb, // rgb input
output reg [2:0] cg_out // chroma out
);
localparam CARRIER_WIDTH =
(CLK_FREQ == 14_000_000)? 17 :
(CLK_FREQ == 14_318_180)? 17 :
(CLK_FREQ == 16_000_000)? 14 :
(CLK_FREQ == 17_734_475)? 3 :
(CLK_FREQ == 20_000_000)? 14 :
(CLK_FREQ == 24_000_000)? 17 :
(CLK_FREQ == 25_000_000)? 16 :
(CLK_FREQ == 28_000_000)? 18 :
(CLK_FREQ == 32_000_000)? 15 :
(CLK_FREQ == 40_000_000)? 15 :
0;
localparam PAL_CARRIER =
(CLK_FREQ == 14_000_000)? 83018 : // 20.776 error
(CLK_FREQ == 14_318_180)? 81173 : // 11.72 error
(CLK_FREQ == 16_000_000)? 9080 : // 25 error
(CLK_FREQ == 17_734_475)? 4 : // 0 error
(CLK_FREQ == 20_000_000)? 7264 : // 25 error
(CLK_FREQ == 24_000_000)? 48427 : // 5.51 error
(CLK_FREQ == 25_000_000)? 23245 : // 13.14 error
(CLK_FREQ == 28_000_000)? 83018 : // 20.78 error
(CLK_FREQ == 32_000_000)? 9080 : // 25 error
(CLK_FREQ == 40_000_000)? 7264 : // 25 error
0;
localparam NTSC_CARRIER =
(CLK_FREQ == 14_000_000)? 67025 : // 23.82 error
(CLK_FREQ == 14_318_180)? 65536 : // 0 errror
(CLK_FREQ == 16_000_000)? 7331 : // 44.84 error
(CLK_FREQ == 17_734_475)? 4 : // 0 error (NTSC4.43)
(CLK_FREQ == 20_000_000)? 5865 : // 166.91 error
(CLK_FREQ == 24_000_000)? 39098 : // 16.19 error
(CLK_FREQ == 25_000_000)? 18767 : // 23.82 error
(CLK_FREQ == 28_000_000)? 67025 : // 23.82 error
(CLK_FREQ == 32_000_000)? 7331 : // 44.84 error
(CLK_FREQ == 40_000_000)? 5865 : // 166.91 error
0;
reg [CARRIER_WIDTH:0] carrier;
wire [31:0] carrier_next;
reg [3:0] burst_cnt;
wire burst;
reg oddeven;
reg [3:0] phase;
reg [3:0] scarrier;
wire cenable;
// DDS for PAL-carrier
assign carrier_next = (cg_pnsel == 1'b0)?
(carrier + PAL_CARRIER) :
(carrier + NTSC_CARRIER) ;
always @(posedge cg_clock) begin
carrier <= carrier_next[CARRIER_WIDTH:0];
end
// burst generator
always @(posedge carrier[CARRIER_WIDTH] or negedge cg_hsync) begin
if (cg_hsync == 1'b0)
burst_cnt <= 4'b0100;
else if (burst_cnt != 4'b0000)
burst_cnt <= burst_cnt + 1'b1;
end
assign burst = burst_cnt[3];
// odd/even line
always @(posedge cg_hsync) begin
if (cg_pnsel == 1'b0)
oddeven <= ~oddeven;
else
oddeven <= 1'b0;
end
// carrier phase
always @* begin
if (burst == 1'b1) begin
if ((oddeven == 1'b0) && (cg_pnsel == 1'b0))
phase <= 4'b0110; // burst phase 135 deg
else
phase <= 4'b1010; // burst phase -135 deg
end
else if (oddeven == 1'b0) begin
case (cg_rgb)
3'b001: phase <= 4'b0000; // blue phase
3'b010: phase <= 4'b0101; // red phase
3'b011: phase <= 4'b0011; // magenta phase
3'b100: phase <= 4'b1011; // green phase
3'b101: phase <= 4'b1101; // cyan phase
3'b110: phase <= 4'b0111; // yellow phase
default: phase <= 4'b0000; // dummy function
endcase
end
else begin
case (cg_rgb)
3'b001: phase <= 4'b0000; // blue phase
3'b010: phase <= 4'b1011; // red phase
3'b011: phase <= 4'b1101; // magenta phase
3'b100: phase <= 4'b0101; // green phase
3'b101: phase <= 4'b0011; // cyan phase
3'b110: phase <= 4'b1001; // yellow phase
default: phase <= 4'b0000; // dummy function
endcase
end
end
// modulated carrier
always @*
scarrier <= carrier[CARRIER_WIDTH:CARRIER_WIDTH-3] + phase;
// colour enable
assign cenable =
cg_enable == 1'b1 &&
cg_rgb != 3'b000 &&
cg_rgb != 3'b111;
// chroma signal
always @(posedge cg_clock) begin
cg_out[2] <= cenable;
cg_out[1] <= burst;
cg_out[0] <= scarrier[3];
end
endmodule

168
cpld/chroma_gen16.vhd
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@ -1,168 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Joerg Wolfram
--
-- Create Date: 04.03.2007
-- Design Name:
-- Module Name: chroma generator
-- Project Name: fbas-encoder
-- Target Device:
-- Tool versions:
-- Description: generates the chroma component of the signal
--
-- Revision: 0.31
-- License: GPL
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity chroma_gen is
port (
-------------------------------------------------------------------------------
--- io
-------------------------------------------------------------------------------
cg_clock: in std_logic; --- input clock
cg_enable: in std_logic; --- colour enable
cg_hsync: in std_logic; --- hor. sync
cg_pnsel: in std_logic; --- system (pal/ntsc)
cg_rgb: in std_logic_vector(2 downto 0); --- rgb input
cg_out: out std_logic_vector(2 downto 0)); --- chroma out
end entity chroma_gen;
---############################################################################
--- 16MHz
---############################################################################
architecture clock16 of chroma_gen is
signal carrier: std_logic_vector(14 downto 0);
signal bcounter: std_logic_vector(3 downto 0);
signal phase: std_logic_vector(3 downto 0);
signal scarrier: std_logic_vector(3 downto 0);
signal oddeven: std_logic;
signal burst,bstop: std_logic;
signal cenable: std_logic;
begin
-------------------------------------------------------------------------------
--- DDS for PAL-carrier
-------------------------------------------------------------------------------
process (cg_clock) is
begin
if (rising_edge(cg_clock)) then
if (cg_pnsel='0') then
carrier <= carrier + 9080;
else
carrier <= carrier + 7331;
end if;
end if;
end process;
-------------------------------------------------------------------------------
--- burst generator
-------------------------------------------------------------------------------
process (bcounter) is
begin
if (bcounter="0000") then
bstop <= '1';
else
bstop <= '0';
end if;
end process;
process (cg_hsync,bstop,carrier(14)) is
begin
if (cg_hsync='0') then
bcounter <= "0100";
elsif ((rising_edge(carrier(14))) and (bstop='0')) then
bcounter <= bcounter + 1;
end if;
end process;
burst <= bcounter(3);
-------------------------------------------------------------------------------
--- odd/even line
-------------------------------------------------------------------------------
process (cg_hsync,cg_pnsel) is
begin
if (rising_edge(cg_hsync)) then
if (cg_pnsel='0') then
oddeven <= not(oddeven);
else
oddeven <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
--- carrier phase
-------------------------------------------------------------------------------
process (cg_rgb,burst,oddeven) is
begin
if (burst='1') then
if ((oddeven = '0') and (cg_pnsel='0')) then
phase <= "0110"; --- burst phase 135 deg
else
phase <= "1010"; --- burst phase -135 deg
end if;
else
if (oddeven = '0') then
case (cg_rgb) is
when "001" => phase <= "0000"; --- blue phase
when "010" => phase <= "0101"; --- red phase
when "011" => phase <= "0011"; --- magenta phase
when "100" => phase <= "1011"; --- green phase
when "101" => phase <= "1101"; --- cyan phase
when "110" => phase <= "0111"; --- yellow phase
when others => phase <= "0000"; --- dummy function
end case;
else
case (cg_rgb) is
when "001" => phase <= "0000"; --- blue phase
when "010" => phase <= "1011"; --- red phase
when "011" => phase <= "1101"; --- magenta phase
when "100" => phase <= "0101"; --- green phase
when "101" => phase <= "0011"; --- cyan phase
when "110" => phase <= "1001"; --- yellow phase
when others => phase <= "0000"; --- dummy function
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------
--- modulated carrier
-------------------------------------------------------------------------------
scarrier <= carrier(14 downto 11) + phase;
-------------------------------------------------------------------------------
--- colour enable
-------------------------------------------------------------------------------
process (cg_rgb,cg_enable) is
begin
if ((cg_rgb/="000") and (cg_rgb/="111") and (cg_enable='1')) then
cenable <= '1';
else
cenable <= '0';
end if;
end process;
-------------------------------------------------------------------------------
--- chroma signal
-------------------------------------------------------------------------------
process (cg_clock) is
begin
if (rising_edge(cg_clock)) then
cg_out(2) <= cenable;
cg_out(1) <= burst;
cg_out(0) <= scarrier(3);
end if;
end process;
end architecture clock16;

2
cpld/top.v
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@ -227,7 +227,7 @@ assign ay_clk = hc[1];
/* VIDEO */
reg [2:0] chroma0;
chroma_gen chroma_gen1(
chroma_gen #(.CLK_FREQ(16_000_000)) chroma_gen1(
.cg_clock(clk16),
.cg_rgb({g,r,b}),
.cg_hsync(hsync1),

2
cpld/zx_ula.qsf
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@ -132,5 +132,5 @@ set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VHDL_FILE chroma_gen16.vhd
set_global_assignment -name VERILOG_FILE chroma_gen.v
set_global_assignment -name VERILOG_FILE top.v

2
cpld_tb/Makefile
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@ -3,7 +3,7 @@ export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/mod
all: testbench_zx_ula
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
testbench_zx_ula: V=$@.v ../cpld/chroma_gen16.vhd
testbench_zx_ula: V=$@.v ../cpld/chroma_gen.v
testbench_memcontroller: V=testbench_memcontroller.v