uzix/zx-sizif-128
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rewrite chroma_gen in verilog

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UzixLS
2020-10-08 22:44:40 +03:00
parent 7d4d9fd525
commit 6369747d58
5 changed files with 140 additions and 171 deletions
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2
cpld_tb/Makefile
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@ -3,7 +3,7 @@ export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/mod
all: testbench_zx_ula
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
testbench_zx_ula: V=$@.v ../cpld/chroma_gen16.vhd
testbench_zx_ula: V=$@.v ../cpld/chroma_gen.v
testbench_memcontroller: V=testbench_memcontroller.v