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rewrite chroma_gen in verilog
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@ -132,5 +132,5 @@ set_global_assignment -name SLOW_SLEW_RATE OFF
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name VHDL_FILE chroma_gen16.vhd
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set_global_assignment -name VERILOG_FILE chroma_gen.v
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set_global_assignment -name VERILOG_FILE top.v
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