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mirror of https://github.com/UzixLS/zx-sizif-128.git synced 2025-07-19 07:11:43 +03:00

rewrite chroma_gen in verilog

This commit is contained in:
UzixLS
2020-10-08 22:44:40 +03:00
parent 7d4d9fd525
commit 6369747d58
5 changed files with 140 additions and 171 deletions

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@ -132,5 +132,5 @@ set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VHDL_FILE chroma_gen16.vhd
set_global_assignment -name VERILOG_FILE chroma_gen.v
set_global_assignment -name VERILOG_FILE top.v