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.gitignore vendored Executable file → Normal file
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42
LICENSE
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@ -1,21 +1,21 @@
MIT License
Copyright (c) 2020 Eugene Lozovoy
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
MIT License
Copyright (c) 2020 Eugene Lozovoy
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

30
README.md
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Cheap compact ZX Spectrum CPLD-based clone.
Specifications:
- CPLD EPM7128SLC84 (128 macrocells)
- Z80 3.5 (3.5795) MHz
- 128K RAM
- AY-8910 (YM2149) mono sound
- Pentagon timings
- PAL encoder in CPLD
- Intended to build on 9x15 prototyping board, but may be built on manufactured PCB
To modify and compile CPLD firmware you need Quartus 13.0sp1.
To modify schematic and pcb you need Kicad 5.1.4 or newer.
[Some photos](https://cloud.err200.net/index.php/s/73TR85tYZkMm8Ax?path=%2Fsizif-128)
Cheap compact ZX Spectrum CPLD-based clone.
Specifications:
- CPLD EPM7128SLC84 (128 macrocells)
- Z80 3.5 (3.5795) MHz
- 128K RAM
- AY-8910 (YM2149) mono sound
- Pentagon timings
- PAL encoder in CPLD
- Intended to build on 9x15 prototyping board, but may be built on manufactured PCB
To modify and compile CPLD firmware you need Quartus 13.0sp1.
To modify schematic and pcb you need Kicad 5.1.4 or newer.
[Some photos](https://cloud.err200.net/index.php/s/73TR85tYZkMm8Ax?path=%2Fsizif-128)

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cpld/clocks.sdc
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create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
create_clock -period 16MHz -name {clk_16mhz} [get_ports {clk16}]
# clkcpu 3.5
create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk14}] [get_registers {hc0[1]}]
# int len in turbo = 66
create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
# chroma carrier
create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk16}] [get_registers {*:chroma_gen1|carrier[14]}]
set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_16mhz}]
set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_16mhz}]
set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_16mhz}]
set_false_path -from [get_registers {hsync1}] -to [get_clocks {chroma_carrier}]
create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
create_clock -period 16MHz -name {clk_16mhz} [get_ports {clk16}]
# clkcpu 3.5
create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk14}] [get_registers {hc0[1]}]
# int len in turbo = 66
create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
# chroma carrier
create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk16}] [get_registers {*:chroma_gen1|carrier[14]}]
set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_16mhz}]
set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_16mhz}]
set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_16mhz}]
set_false_path -from [get_registers {hsync1}] -to [get_clocks {chroma_carrier}]

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cpld/top.v Executable file → Normal file
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module zx_ula(
input rst_n,
input clk14,
input clk16,
output clkcpu,
inout [7:0] vd,
inout [16:0] va,
output ra14,
input a0,
input a1,
input a14,
input a15,
input n_rd,
input n_wr,
input n_mreq,
input n_iorq,
input n_m1,
input n_rfsh,
output reg n_int,
output n_vrd,
output n_vwr,
output reg n_romcs,
input [4:0] kd,
input tape_in,
output tape_out,
output reg beeper,
output ay_clk,
output reg ay_bdir,
output reg ay_bc1,
output reg r,
output reg g,
output reg b,
output reg i,
output [1:0] chroma,
output reg csync
);
wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
wire [7:0] xd = vd;
reg n_iorq_delayed;
always @(posedge clkcpu)
n_iorq_delayed <= n_iorq;
wire n_iorq0 = n_iorq | n_iorq_delayed;
/* SCREEN CONTROLLER */
localparam H_AREA = 256;
localparam V_AREA = 192;
localparam SCREEN_DELAY = 8;
localparam H_TOTAL = 448;
localparam V_TOTAL = 320;
reg [$clog2(V_TOTAL)-1:0] vc;
reg [$clog2(H_TOTAL):0] hc0;
wire [$clog2(H_TOTAL)-1:0] hc = hc0[$bits(hc0)-1:1];
wire hc0_reset = hc0 == (H_TOTAL<<1) - 1'b1 ;
wire vc_reset = vc == V_TOTAL - 1'b1 ;
wire hsync0 = hc[8:5] == 4'b1010;
wire vsync0 = vc[7:3] == 5'b11111;
wire blank = (vc[7:3] == 5'b11111) || (hc[8:6] == 3'b101);
reg hsync1;
always @(posedge clk14)
hsync1 = hc[8:5] != 4'b1010;
always @(posedge clk14) begin
if (hc0_reset) begin
hc0 <= 0;
if (vc_reset) begin
vc <= 0;
end
else begin
vc <= vc + 1'b1;
end
end
else begin
hc0 <= hc0 + 1'b1;
end
end
reg [4:0] blink_cnt;
wire blink = blink_cnt[$bits(blink_cnt)-1];
always @(posedge n_int or negedge rst_n) begin
if (!rst_n)
blink_cnt <= 0;
else
blink_cnt <= blink_cnt + 1'b1;
end
reg [2:0] border;
reg [7:0] bitmap, attr, bitmap_next, attr_next;
reg screen_read;
wire attr_read = screen_read & ~hc0[0];
wire bitmap_read = screen_read & hc0[0];
wire [14:0] bitmap_addr = { 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] };
wire [14:0] attr_addr = { 5'b10110, vc[7:3], hc[7:3] };
wire [14:0] screen_addr = attr_read? attr_addr : bitmap_addr;
wire screen_load = (vc < V_AREA) && (hc < H_AREA);
wire screen_show = (vc < V_AREA) && (hc >= SCREEN_DELAY) && (hc < H_AREA + SCREEN_DELAY);
wire screen_update = hc0[3:0] == 4'b1111;
wire border_update = (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0);
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
screen_read <= 0;
attr <= 0;
bitmap <= 0;
attr_next <= 0;
bitmap_next <= 0;
end
else begin
screen_read <= screen_load && (n_mreq == 1 && n_iorq == 1);
if (attr_read)
attr_next <= vd;
if (bitmap_read)
bitmap_next <= vd;
if (screen_load && screen_update)
attr <= attr_next;
else if (border_update)
attr <= {2'b00, border, 3'b000};
if (screen_load && screen_update)
bitmap <= bitmap_next;
else if (hc0[0])
bitmap <= {bitmap[6:0], 1'b0};
end
end
wire pixel = bitmap[7];
always @(posedge clk14) begin
if (hc0[0]) begin
if (blank)
{i, g, r, b} = 4'b0000;
else begin
{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
i = (g | r | b) & attr[6];
end
csync <= ~(vsync0 ^ hsync0);
end
end
/* CLOCK */
assign clkcpu = hc[0];
/* INT GENERATOR */
localparam INT_V = 239;
localparam INT_H_FROM = 318;
localparam INT_H_TO = 382;
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n)
n_int <= 1;
else
n_int <= vc != INT_V || hc < INT_H_FROM || hc > INT_H_TO ;
end
/* PORT #FE */
wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
reg port_fe_rd;
always @(posedge clk14)
port_fe_rd <= port_fe_cs && n_rd == 0;
reg tape_out0;
assign tape_out = tape_in ^ tape_out0;
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
beeper <= 0;
tape_out0 <= 0;
border <= 0;
end
else if (port_fe_cs && n_wr == 0) begin
beeper <= xd[4];
tape_out0 <= xd[3];
border <= xd[2:0];
end
end
/* PORT #7FFD */
wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0 && xa[14] == 1;
reg [2:0] rambank;
reg rombank, vbank, lock_7ffd;
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
rambank <= 0;
vbank <= 0;
rombank <= 0;
lock_7ffd <= 0;
end
else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0) begin
rambank <= xd[2:0];
vbank <= xd[3];
rombank <= xd[4];
lock_7ffd <= xd[5];
end
end
/* AY */
always @(posedge clkcpu or negedge rst_n) begin
if (!rst_n) begin
ay_bc1 <= 0;
ay_bdir <= 0;
end
else begin
ay_bc1 <= xa[15] == 1 && xa[14] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0;
ay_bdir <= xa[15] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0 && n_wr == 0;
end
end
assign ay_clk = hc[1];
/* VIDEO */
reg [2:0] chroma0;
chroma_gen #(.CLK_FREQ(16_000_000)) chroma_gen1(
.cg_clock(clk16),
.cg_rgb({g,r,b}),
.cg_hsync(hsync1),
.cg_enable(1'b1),
.cg_pnsel(1'b0),
.cg_out(chroma0)
);
assign chroma[0] = chroma0[1]? chroma0[0] : 1'bz;
assign chroma[1] = chroma0[2]? chroma0[0] : 1'bz;
/* MEMORY CONTROLLER */
// 7ffe a15-14 va16-14
// xxx 01 010 bank 2
// xxx 10 101 bank 5
// 000 11 000 bank 0
// 001 11 001 bank 1 | contended
// 010 11 010 bank 2
// 011 11 011 bank 3 | contended
// 100 11 100 bank 4
// 101 11 101 bank 5 | contended (video)
// 110 11 110 bank 6
// 111 11 111 bank 7 | contended (video alt)
// 7ffe a15-14 ra14
// 0 00 0 rom0
// 1 00 1 rom1
wire n_vcs_cpu = n_mreq | ~(a15 | a14);
assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1;
assign n_vwr = ((n_vcs_cpu == 0 && n_wr == 0) && screen_read == 0)? 1'b0 : 1'b1;
always @(posedge clkcpu) begin
n_romcs <= n_mreq | a15 | a14;
end
assign ra14 = rombank;
assign va[16:0] =
screen_read? {1'b1, vbank, screen_addr} :
a15 & a14? {rambank, {14{1'bz}}} :
{a14, a15, a14, {14{1'bz}}};
assign vd[7:0] =
port_fe_rd? port_fe_data :
n_iorq0 == 0 && (n_rd == 0 | n_m1 == 0)? {8{1'b1}} :
{8{1'bz}};
endmodule
module zx_ula(
input rst_n,
input clk14,
input clk16,
output clkcpu,
inout [7:0] vd,
inout [16:0] va,
output ra14,
input a0,
input a1,
input a14,
input a15,
input n_rd,
input n_wr,
input n_mreq,
input n_iorq,
input n_m1,
input n_rfsh,
output reg n_int,
output n_vrd,
output n_vwr,
output reg n_romcs,
input [4:0] kd,
input tape_in,
output tape_out,
output reg beeper,
output ay_clk,
output reg ay_bdir,
output reg ay_bc1,
output reg r,
output reg g,
output reg b,
output reg i,
output [1:0] chroma,
output reg csync
);
wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
wire [7:0] xd = vd;
reg n_iorq_delayed;
always @(posedge clkcpu)
n_iorq_delayed <= n_iorq;
wire n_iorq0 = n_iorq | n_iorq_delayed;
/* SCREEN CONTROLLER */
localparam H_AREA = 256;
localparam V_AREA = 192;
localparam SCREEN_DELAY = 8;
localparam H_TOTAL = 448;
localparam V_TOTAL = 320;
reg [$clog2(V_TOTAL)-1:0] vc;
reg [$clog2(H_TOTAL):0] hc0;
wire [$clog2(H_TOTAL)-1:0] hc = hc0[$bits(hc0)-1:1];
wire hc0_reset = hc0 == (H_TOTAL<<1) - 1'b1 ;
wire vc_reset = vc == V_TOTAL - 1'b1 ;
wire hsync0 = hc[8:5] == 4'b1010;
wire vsync0 = vc[7:3] == 5'b11111;
wire blank = (vc[7:3] == 5'b11111) || (hc[8:6] == 3'b101);
reg hsync1;
always @(posedge clk14)
hsync1 = hc[8:5] != 4'b1010;
always @(posedge clk14) begin
if (hc0_reset) begin
hc0 <= 0;
if (vc_reset) begin
vc <= 0;
end
else begin
vc <= vc + 1'b1;
end
end
else begin
hc0 <= hc0 + 1'b1;
end
end
reg [4:0] blink_cnt;
wire blink = blink_cnt[$bits(blink_cnt)-1];
always @(posedge n_int or negedge rst_n) begin
if (!rst_n)
blink_cnt <= 0;
else
blink_cnt <= blink_cnt + 1'b1;
end
reg [2:0] border;
reg [7:0] bitmap, attr, bitmap_next, attr_next;
reg screen_read;
wire attr_read = screen_read & ~hc0[0];
wire bitmap_read = screen_read & hc0[0];
wire [14:0] bitmap_addr = { 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] };
wire [14:0] attr_addr = { 5'b10110, vc[7:3], hc[7:3] };
wire [14:0] screen_addr = attr_read? attr_addr : bitmap_addr;
wire screen_load = (vc < V_AREA) && (hc < H_AREA);
wire screen_show = (vc < V_AREA) && (hc >= SCREEN_DELAY) && (hc < H_AREA + SCREEN_DELAY);
wire screen_update = hc0[3:0] == 4'b1111;
wire border_update = (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0);
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
screen_read <= 0;
attr <= 0;
bitmap <= 0;
attr_next <= 0;
bitmap_next <= 0;
end
else begin
screen_read <= screen_load && (n_mreq == 1 && n_iorq == 1);
if (attr_read)
attr_next <= vd;
if (bitmap_read)
bitmap_next <= vd;
if (screen_load && screen_update)
attr <= attr_next;
else if (border_update)
attr <= {2'b00, border, 3'b000};
if (screen_load && screen_update)
bitmap <= bitmap_next;
else if (hc0[0])
bitmap <= {bitmap[6:0], 1'b0};
end
end
wire pixel = bitmap[7];
always @(posedge clk14) begin
if (hc0[0]) begin
if (blank)
{i, g, r, b} = 4'b0000;
else begin
{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
i = (g | r | b) & attr[6];
end
csync <= ~(vsync0 ^ hsync0);
end
end
/* CLOCK */
assign clkcpu = hc[0];
/* INT GENERATOR */
localparam INT_V = 239;
localparam INT_H_FROM = 318;
localparam INT_H_TO = 382;
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n)
n_int <= 1;
else
n_int <= vc != INT_V || hc < INT_H_FROM || hc > INT_H_TO ;
end
/* PORT #FE */
wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
reg port_fe_rd;
always @(posedge clk14)
port_fe_rd <= port_fe_cs && n_rd == 0;
reg tape_out0;
assign tape_out = tape_in ^ tape_out0;
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
beeper <= 0;
tape_out0 <= 0;
border <= 0;
end
else if (port_fe_cs && n_wr == 0) begin
beeper <= xd[4];
tape_out0 <= xd[3];
border <= xd[2:0];
end
end
/* PORT #7FFD */
wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0 && xa[14] == 1;
reg [2:0] rambank;
reg rombank, vbank, lock_7ffd;
always @(posedge clk14 or negedge rst_n) begin
if (!rst_n) begin
rambank <= 0;
vbank <= 0;
rombank <= 0;
lock_7ffd <= 0;
end
else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0) begin
rambank <= xd[2:0];
vbank <= xd[3];
rombank <= xd[4];
lock_7ffd <= xd[5];
end
end
/* AY */
always @(posedge clkcpu or negedge rst_n) begin
if (!rst_n) begin
ay_bc1 <= 0;
ay_bdir <= 0;
end
else begin
ay_bc1 <= xa[15] == 1 && xa[14] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0;
ay_bdir <= xa[15] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0 && n_wr == 0;
end
end
assign ay_clk = hc[1];
/* VIDEO */
reg [2:0] chroma0;
chroma_gen #(.CLK_FREQ(16_000_000)) chroma_gen1(
.cg_clock(clk16),
.cg_rgb({g,r,b}),
.cg_hsync(hsync1),
.cg_enable(1'b1),
.cg_pnsel(1'b0),
.cg_out(chroma0)
);
assign chroma[0] = chroma0[1]? chroma0[0] : 1'bz;
assign chroma[1] = chroma0[2]? chroma0[0] : 1'bz;
/* MEMORY CONTROLLER */
// 7ffe a15-14 va16-14
// xxx 01 010 bank 2
// xxx 10 101 bank 5
// 000 11 000 bank 0
// 001 11 001 bank 1 | contended
// 010 11 010 bank 2
// 011 11 011 bank 3 | contended
// 100 11 100 bank 4
// 101 11 101 bank 5 | contended (video)
// 110 11 110 bank 6
// 111 11 111 bank 7 | contended (video alt)
// 7ffe a15-14 ra14
// 0 00 0 rom0
// 1 00 1 rom1
wire n_vcs_cpu = n_mreq | ~(a15 | a14);
assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1;
assign n_vwr = ((n_vcs_cpu == 0 && n_wr == 0) && screen_read == 0)? 1'b0 : 1'b1;
always @(posedge clkcpu) begin
n_romcs <= n_mreq | a15 | a14;
end
assign ra14 = rombank;
assign va[16:0] =
screen_read? {1'b1, vbank, screen_addr} :
a15 & a14? {rambank, {14{1'bz}}} :
{a14, a15, a14, {14{1'bz}}};
assign vd[7:0] =
port_fe_rd? port_fe_data :
n_iorq0 == 0 && (n_rd == 0 | n_m1 == 0)? {8{1'b1}} :
{8{1'bz}};
endmodule

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@ -1,30 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"

270
cpld/zx_ula.qsf Executable file → Normal file
View File

@ -1,136 +1,136 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_10 -to b
set_location_assignment PIN_4 -to beeper
set_location_assignment PIN_83 -to clk14
set_location_assignment PIN_21 -to clkcpu
set_location_assignment PIN_5 -to g
set_location_assignment PIN_18 -to n_int
set_location_assignment PIN_24 -to n_iorq
set_location_assignment PIN_22 -to n_m1
set_location_assignment PIN_25 -to n_mreq
set_location_assignment PIN_31 -to n_rd
set_location_assignment PIN_20 -to n_rfsh
set_location_assignment PIN_30 -to n_romcs
set_location_assignment PIN_45 -to n_vrd
set_location_assignment PIN_73 -to n_vwr
set_location_assignment PIN_29 -to n_wr
set_location_assignment PIN_8 -to r
set_location_assignment PIN_1 -to rst_n
set_location_assignment PIN_81 -to tape_out
set_location_assignment PIN_48 -to va[16]
set_location_assignment PIN_64 -to va[15]
set_location_assignment PIN_61 -to va[14]
set_location_assignment PIN_67 -to va[13]
set_location_assignment PIN_69 -to va[12]
set_location_assignment PIN_70 -to va[11]
set_location_assignment PIN_75 -to va[10]
set_location_assignment PIN_76 -to va[9]
set_location_assignment PIN_74 -to va[8]
set_location_assignment PIN_65 -to va[7]
set_location_assignment PIN_77 -to va[6]
set_location_assignment PIN_46 -to va[5]
set_location_assignment PIN_44 -to va[4]
set_location_assignment PIN_63 -to va[3]
set_location_assignment PIN_68 -to va[2]
set_location_assignment PIN_60 -to va[1]
set_location_assignment PIN_58 -to va[0]
set_location_assignment PIN_51 -to vd[7]
set_location_assignment PIN_55 -to vd[6]
set_location_assignment PIN_54 -to vd[5]
set_location_assignment PIN_57 -to vd[4]
set_location_assignment PIN_56 -to vd[3]
set_location_assignment PIN_52 -to vd[2]
set_location_assignment PIN_49 -to vd[1]
set_location_assignment PIN_50 -to vd[0]
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
set_location_assignment PIN_6 -to i
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_location_assignment PIN_28 -to a0
set_location_assignment PIN_27 -to a1
set_location_assignment PIN_17 -to a14
set_location_assignment PIN_16 -to a15
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_location_assignment PIN_9 -to csync
set_location_assignment PIN_2 -to clk16
set_location_assignment PIN_11 -to chroma[1]
set_location_assignment PIN_12 -to chroma[0]
set_location_assignment PIN_33 -to kd[1]
set_location_assignment PIN_34 -to kd[0]
set_location_assignment PIN_35 -to kd[3]
set_location_assignment PIN_36 -to kd[2]
set_location_assignment PIN_37 -to kd[4]
set_location_assignment PIN_39 -to ay_bc1
set_location_assignment PIN_40 -to ay_bdir
set_location_assignment PIN_41 -to ay_clk
set_location_assignment PIN_79 -to tape_in
set_location_assignment PIN_80 -to ra14
set_global_assignment -name FMAX_REQUIREMENT "16 MHz" -section_id clk16
set_instance_assignment -name CLOCK_SETTINGS clk16 -to clk16
set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE chroma_gen.v
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_10 -to b
set_location_assignment PIN_4 -to beeper
set_location_assignment PIN_83 -to clk14
set_location_assignment PIN_21 -to clkcpu
set_location_assignment PIN_5 -to g
set_location_assignment PIN_18 -to n_int
set_location_assignment PIN_24 -to n_iorq
set_location_assignment PIN_22 -to n_m1
set_location_assignment PIN_25 -to n_mreq
set_location_assignment PIN_31 -to n_rd
set_location_assignment PIN_20 -to n_rfsh
set_location_assignment PIN_30 -to n_romcs
set_location_assignment PIN_45 -to n_vrd
set_location_assignment PIN_73 -to n_vwr
set_location_assignment PIN_29 -to n_wr
set_location_assignment PIN_8 -to r
set_location_assignment PIN_1 -to rst_n
set_location_assignment PIN_81 -to tape_out
set_location_assignment PIN_48 -to va[16]
set_location_assignment PIN_64 -to va[15]
set_location_assignment PIN_61 -to va[14]
set_location_assignment PIN_67 -to va[13]
set_location_assignment PIN_69 -to va[12]
set_location_assignment PIN_70 -to va[11]
set_location_assignment PIN_75 -to va[10]
set_location_assignment PIN_76 -to va[9]
set_location_assignment PIN_74 -to va[8]
set_location_assignment PIN_65 -to va[7]
set_location_assignment PIN_77 -to va[6]
set_location_assignment PIN_46 -to va[5]
set_location_assignment PIN_44 -to va[4]
set_location_assignment PIN_63 -to va[3]
set_location_assignment PIN_68 -to va[2]
set_location_assignment PIN_60 -to va[1]
set_location_assignment PIN_58 -to va[0]
set_location_assignment PIN_51 -to vd[7]
set_location_assignment PIN_55 -to vd[6]
set_location_assignment PIN_54 -to vd[5]
set_location_assignment PIN_57 -to vd[4]
set_location_assignment PIN_56 -to vd[3]
set_location_assignment PIN_52 -to vd[2]
set_location_assignment PIN_49 -to vd[1]
set_location_assignment PIN_50 -to vd[0]
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
set_location_assignment PIN_6 -to i
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_location_assignment PIN_28 -to a0
set_location_assignment PIN_27 -to a1
set_location_assignment PIN_17 -to a14
set_location_assignment PIN_16 -to a15
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_location_assignment PIN_9 -to csync
set_location_assignment PIN_2 -to clk16
set_location_assignment PIN_11 -to chroma[1]
set_location_assignment PIN_12 -to chroma[0]
set_location_assignment PIN_33 -to kd[1]
set_location_assignment PIN_34 -to kd[0]
set_location_assignment PIN_35 -to kd[3]
set_location_assignment PIN_36 -to kd[2]
set_location_assignment PIN_37 -to kd[4]
set_location_assignment PIN_39 -to ay_bc1
set_location_assignment PIN_40 -to ay_bdir
set_location_assignment PIN_41 -to ay_clk
set_location_assignment PIN_79 -to tape_in
set_location_assignment PIN_80 -to ra14
set_global_assignment -name FMAX_REQUIREMENT "16 MHz" -section_id clk16
set_instance_assignment -name CLOCK_SETTINGS clk16 -to clk16
set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE chroma_gen.v
set_global_assignment -name VERILOG_FILE top.v

52
cpld_tb/Makefile
View File

@ -1,26 +1,26 @@
export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:${PATH}
all: testbench_zx_ula
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
testbench_zx_ula: V=$@.v ../cpld/chroma_gen.v
testbench_memcontroller: V=testbench_memcontroller.v
xtestbench_%:
iverilog -g2005-sv ${IVFLAGS} -o $@.vvp ${V}
vvp $@.vvp
@rm $@.vvp
testbench_%:
test ! -d work || rm -rf work
vlib work
test ! -n "$(filter %.v,${V})" || vlog -quiet -sv $(filter %.v,${V})
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
vsim ${VSIMFLAGS} -batch -quiet -do 'run -all' $@
test ! -r transcript || rm transcript
clean:
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
-include Makefile.local
export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:${PATH}
all: testbench_zx_ula
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
testbench_zx_ula: V=$@.v ../cpld/chroma_gen.v
testbench_memcontroller: V=testbench_memcontroller.v
xtestbench_%:
iverilog -g2005-sv ${IVFLAGS} -o $@.vvp ${V}
vvp $@.vvp
@rm $@.vvp
testbench_%:
test ! -d work || rm -rf work
vlib work
test ! -n "$(filter %.v,${V})" || vlog -quiet -sv $(filter %.v,${V})
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
vsim ${VSIMFLAGS} -batch -quiet -do 'run -all' $@
test ! -r transcript || rm transcript
clean:
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
-include Makefile.local

100
cpld_tb/testbench_zx_ula.v
View File

@ -1,50 +1,50 @@
`define USE_FPGA
`include "../cpld/top.v"
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk14;
/* ULA */
zx_ula zx_ula1(
.rst_n(rst_n),
.clk14(clk14)
);
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk14 = 0;
#357 clk14 = 1;
#358;
end
initial zx_ula1.hc0 = 0;
initial zx_ula1.vc = 0;
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk14) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule
`define USE_FPGA
`include "../cpld/top.v"
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk14;
/* ULA */
zx_ula zx_ula1(
.rst_n(rst_n),
.clk14(clk14)
);
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk14 = 0;
#357 clk14 = 1;
#358;
end
initial zx_ula1.hc0 = 0;
initial zx_ula1.vc = 0;
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk14) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule

1608
pcb/rev.A/sizif128-cache.lib
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File diff suppressed because it is too large Load Diff

24426
pcb/rev.A/sizif128.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

544
pcb/rev.A/sizif128.pro
View File

@ -1,272 +1,272 @@
update=19/04/2020 12:29:46
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.55
TrackWidth3=1
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.3
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=E:/ws/kicad-lib/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
update=19/04/2020 12:29:46
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.55
TrackWidth3=1
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.3
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=E:/ws/kicad-lib/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

6222
pcb/rev.A/sizif128.sch
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