uzix/zx-sizif-128
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git: fix CRLF

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UzixLS
2020-10-12 13:33:30 +03:00
parent 6369747d58
commit 54709babeb
13 changed files with 16971 additions and 16971 deletions
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52
cpld_tb/Makefile
View File

@ -1,26 +1,26 @@
export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:${PATH}
all: testbench_zx_ula
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
testbench_zx_ula: V=$@.v ../cpld/chroma_gen.v
testbench_memcontroller: V=testbench_memcontroller.v
xtestbench_%:
iverilog -g2005-sv ${IVFLAGS} -o $@.vvp ${V}
vvp $@.vvp
@rm $@.vvp
testbench_%:
test ! -d work || rm -rf work
vlib work
test ! -n "$(filter %.v,${V})" || vlog -quiet -sv $(filter %.v,${V})
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
vsim ${VSIMFLAGS} -batch -quiet -do 'run -all' $@
test ! -r transcript || rm transcript
clean:
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
-include Makefile.local
export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:${PATH}
all: testbench_zx_ula
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
testbench_zx_ula: V=$@.v ../cpld/chroma_gen.v
testbench_memcontroller: V=testbench_memcontroller.v
xtestbench_%:
iverilog -g2005-sv ${IVFLAGS} -o $@.vvp ${V}
vvp $@.vvp
@rm $@.vvp
testbench_%:
test ! -d work || rm -rf work
vlib work
test ! -n "$(filter %.v,${V})" || vlog -quiet -sv $(filter %.v,${V})
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
vsim ${VSIMFLAGS} -batch -quiet -do 'run -all' $@
test ! -r transcript || rm transcript
clean:
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
-include Makefile.local

100
cpld_tb/testbench_zx_ula.v
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@ -1,50 +1,50 @@
`define USE_FPGA
`include "../cpld/top.v"
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk14;
/* ULA */
zx_ula zx_ula1(
.rst_n(rst_n),
.clk14(clk14)
);
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk14 = 0;
#357 clk14 = 1;
#358;
end
initial zx_ula1.hc0 = 0;
initial zx_ula1.vc = 0;
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk14) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule
`define USE_FPGA
`include "../cpld/top.v"
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk14;
/* ULA */
zx_ula zx_ula1(
.rst_n(rst_n),
.clk14(clk14)
);
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk14 = 0;
#357 clk14 = 1;
#358;
end
initial zx_ula1.hc0 = 0;
initial zx_ula1.vc = 0;
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk14) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule