mirror of
https://github.com/UzixLS/zx-sizif-128.git
synced 2025-07-18 23:01:28 +03:00
git: fix CRLF
This commit is contained in:
UzixLS
@ -1,16 +1,16 @@
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create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
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create_clock -period 16MHz -name {clk_16mhz} [get_ports {clk16}]
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# clkcpu 3.5
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create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk14}] [get_registers {hc0[1]}]
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# int len in turbo = 66
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create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
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# chroma carrier
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create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk16}] [get_registers {*:chroma_gen1|carrier[14]}]
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set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {hsync1}] -to [get_clocks {chroma_carrier}]
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create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
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create_clock -period 16MHz -name {clk_16mhz} [get_ports {clk16}]
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# clkcpu 3.5
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create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk14}] [get_registers {hc0[1]}]
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# int len in turbo = 66
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create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
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# chroma carrier
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create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk16}] [get_registers {*:chroma_gen1|carrier[14]}]
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set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {hsync1}] -to [get_clocks {chroma_carrier}]
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556
cpld/top.v
Executable file → Normal file
556
cpld/top.v
Executable file → Normal file
@ -1,278 +1,278 @@
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module zx_ula(
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input rst_n,
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input clk14,
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input clk16,
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output clkcpu,
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inout [7:0] vd,
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inout [16:0] va,
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output ra14,
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input a0,
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input a1,
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input a14,
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input a15,
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input n_rd,
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input n_wr,
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input n_mreq,
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input n_iorq,
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input n_m1,
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input n_rfsh,
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output reg n_int,
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output n_vrd,
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output n_vwr,
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output reg n_romcs,
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input [4:0] kd,
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input tape_in,
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output tape_out,
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output reg beeper,
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output ay_clk,
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output reg ay_bdir,
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output reg ay_bc1,
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output reg r,
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output reg g,
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output reg b,
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output reg i,
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output [1:0] chroma,
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output reg csync
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);
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wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
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wire [7:0] xd = vd;
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reg n_iorq_delayed;
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always @(posedge clkcpu)
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n_iorq_delayed <= n_iorq;
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wire n_iorq0 = n_iorq | n_iorq_delayed;
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/* SCREEN CONTROLLER */
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localparam H_AREA = 256;
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localparam V_AREA = 192;
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localparam SCREEN_DELAY = 8;
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localparam H_TOTAL = 448;
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localparam V_TOTAL = 320;
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reg [$clog2(V_TOTAL)-1:0] vc;
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reg [$clog2(H_TOTAL):0] hc0;
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wire [$clog2(H_TOTAL)-1:0] hc = hc0[$bits(hc0)-1:1];
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wire hc0_reset = hc0 == (H_TOTAL<<1) - 1'b1 ;
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wire vc_reset = vc == V_TOTAL - 1'b1 ;
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wire hsync0 = hc[8:5] == 4'b1010;
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wire vsync0 = vc[7:3] == 5'b11111;
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wire blank = (vc[7:3] == 5'b11111) || (hc[8:6] == 3'b101);
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reg hsync1;
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always @(posedge clk14)
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hsync1 = hc[8:5] != 4'b1010;
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always @(posedge clk14) begin
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if (hc0_reset) begin
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hc0 <= 0;
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if (vc_reset) begin
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vc <= 0;
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end
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else begin
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vc <= vc + 1'b1;
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end
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end
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else begin
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hc0 <= hc0 + 1'b1;
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end
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end
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reg [4:0] blink_cnt;
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wire blink = blink_cnt[$bits(blink_cnt)-1];
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always @(posedge n_int or negedge rst_n) begin
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if (!rst_n)
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blink_cnt <= 0;
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else
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blink_cnt <= blink_cnt + 1'b1;
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end
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reg [2:0] border;
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reg [7:0] bitmap, attr, bitmap_next, attr_next;
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reg screen_read;
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wire attr_read = screen_read & ~hc0[0];
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wire bitmap_read = screen_read & hc0[0];
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wire [14:0] bitmap_addr = { 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] };
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wire [14:0] attr_addr = { 5'b10110, vc[7:3], hc[7:3] };
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wire [14:0] screen_addr = attr_read? attr_addr : bitmap_addr;
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wire screen_load = (vc < V_AREA) && (hc < H_AREA);
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wire screen_show = (vc < V_AREA) && (hc >= SCREEN_DELAY) && (hc < H_AREA + SCREEN_DELAY);
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wire screen_update = hc0[3:0] == 4'b1111;
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wire border_update = (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0);
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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screen_read <= 0;
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attr <= 0;
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bitmap <= 0;
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attr_next <= 0;
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bitmap_next <= 0;
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end
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else begin
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screen_read <= screen_load && (n_mreq == 1 && n_iorq == 1);
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if (attr_read)
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attr_next <= vd;
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if (bitmap_read)
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bitmap_next <= vd;
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if (screen_load && screen_update)
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attr <= attr_next;
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else if (border_update)
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attr <= {2'b00, border, 3'b000};
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if (screen_load && screen_update)
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bitmap <= bitmap_next;
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else if (hc0[0])
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bitmap <= {bitmap[6:0], 1'b0};
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end
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end
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wire pixel = bitmap[7];
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always @(posedge clk14) begin
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if (hc0[0]) begin
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if (blank)
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{i, g, r, b} = 4'b0000;
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else begin
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{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
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i = (g | r | b) & attr[6];
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end
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csync <= ~(vsync0 ^ hsync0);
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end
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end
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/* CLOCK */
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assign clkcpu = hc[0];
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/* INT GENERATOR */
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localparam INT_V = 239;
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localparam INT_H_FROM = 318;
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localparam INT_H_TO = 382;
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n)
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n_int <= 1;
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else
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n_int <= vc != INT_V || hc < INT_H_FROM || hc > INT_H_TO ;
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end
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/* PORT #FE */
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wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
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wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
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reg port_fe_rd;
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always @(posedge clk14)
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port_fe_rd <= port_fe_cs && n_rd == 0;
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reg tape_out0;
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assign tape_out = tape_in ^ tape_out0;
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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beeper <= 0;
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tape_out0 <= 0;
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border <= 0;
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end
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else if (port_fe_cs && n_wr == 0) begin
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beeper <= xd[4];
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tape_out0 <= xd[3];
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border <= xd[2:0];
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end
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end
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/* PORT #7FFD */
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wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0 && xa[14] == 1;
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reg [2:0] rambank;
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reg rombank, vbank, lock_7ffd;
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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rambank <= 0;
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vbank <= 0;
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rombank <= 0;
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lock_7ffd <= 0;
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end
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else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0) begin
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rambank <= xd[2:0];
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vbank <= xd[3];
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rombank <= xd[4];
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lock_7ffd <= xd[5];
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end
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end
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/* AY */
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always @(posedge clkcpu or negedge rst_n) begin
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if (!rst_n) begin
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ay_bc1 <= 0;
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ay_bdir <= 0;
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end
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else begin
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ay_bc1 <= xa[15] == 1 && xa[14] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0;
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ay_bdir <= xa[15] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0 && n_wr == 0;
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end
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end
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assign ay_clk = hc[1];
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/* VIDEO */
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reg [2:0] chroma0;
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chroma_gen #(.CLK_FREQ(16_000_000)) chroma_gen1(
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.cg_clock(clk16),
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.cg_rgb({g,r,b}),
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.cg_hsync(hsync1),
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.cg_enable(1'b1),
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.cg_pnsel(1'b0),
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.cg_out(chroma0)
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);
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assign chroma[0] = chroma0[1]? chroma0[0] : 1'bz;
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assign chroma[1] = chroma0[2]? chroma0[0] : 1'bz;
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/* MEMORY CONTROLLER */
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// 7ffe a15-14 va16-14
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// xxx 01 010 bank 2
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// xxx 10 101 bank 5
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// 000 11 000 bank 0
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// 001 11 001 bank 1 | contended
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// 010 11 010 bank 2
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// 011 11 011 bank 3 | contended
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// 100 11 100 bank 4
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// 101 11 101 bank 5 | contended (video)
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// 110 11 110 bank 6
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// 111 11 111 bank 7 | contended (video alt)
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// 7ffe a15-14 ra14
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// 0 00 0 rom0
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// 1 00 1 rom1
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wire n_vcs_cpu = n_mreq | ~(a15 | a14);
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assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1;
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assign n_vwr = ((n_vcs_cpu == 0 && n_wr == 0) && screen_read == 0)? 1'b0 : 1'b1;
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always @(posedge clkcpu) begin
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n_romcs <= n_mreq | a15 | a14;
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end
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assign ra14 = rombank;
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assign va[16:0] =
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screen_read? {1'b1, vbank, screen_addr} :
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a15 & a14? {rambank, {14{1'bz}}} :
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{a14, a15, a14, {14{1'bz}}};
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assign vd[7:0] =
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port_fe_rd? port_fe_data :
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n_iorq0 == 0 && (n_rd == 0 | n_m1 == 0)? {8{1'b1}} :
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{8{1'bz}};
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endmodule
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module zx_ula(
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input rst_n,
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input clk14,
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input clk16,
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output clkcpu,
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inout [7:0] vd,
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inout [16:0] va,
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output ra14,
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input a0,
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input a1,
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input a14,
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input a15,
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input n_rd,
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input n_wr,
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input n_mreq,
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input n_iorq,
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input n_m1,
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input n_rfsh,
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output reg n_int,
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output n_vrd,
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output n_vwr,
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output reg n_romcs,
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input [4:0] kd,
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input tape_in,
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output tape_out,
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output reg beeper,
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output ay_clk,
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output reg ay_bdir,
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output reg ay_bc1,
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output reg r,
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output reg g,
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output reg b,
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output reg i,
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output [1:0] chroma,
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output reg csync
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);
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wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
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wire [7:0] xd = vd;
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reg n_iorq_delayed;
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always @(posedge clkcpu)
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n_iorq_delayed <= n_iorq;
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wire n_iorq0 = n_iorq | n_iorq_delayed;
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/* SCREEN CONTROLLER */
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localparam H_AREA = 256;
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localparam V_AREA = 192;
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localparam SCREEN_DELAY = 8;
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localparam H_TOTAL = 448;
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localparam V_TOTAL = 320;
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reg [$clog2(V_TOTAL)-1:0] vc;
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reg [$clog2(H_TOTAL):0] hc0;
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wire [$clog2(H_TOTAL)-1:0] hc = hc0[$bits(hc0)-1:1];
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wire hc0_reset = hc0 == (H_TOTAL<<1) - 1'b1 ;
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wire vc_reset = vc == V_TOTAL - 1'b1 ;
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wire hsync0 = hc[8:5] == 4'b1010;
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wire vsync0 = vc[7:3] == 5'b11111;
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wire blank = (vc[7:3] == 5'b11111) || (hc[8:6] == 3'b101);
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reg hsync1;
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always @(posedge clk14)
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hsync1 = hc[8:5] != 4'b1010;
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always @(posedge clk14) begin
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if (hc0_reset) begin
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hc0 <= 0;
|
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if (vc_reset) begin
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vc <= 0;
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end
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else begin
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vc <= vc + 1'b1;
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end
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end
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else begin
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hc0 <= hc0 + 1'b1;
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end
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end
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reg [4:0] blink_cnt;
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wire blink = blink_cnt[$bits(blink_cnt)-1];
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always @(posedge n_int or negedge rst_n) begin
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if (!rst_n)
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blink_cnt <= 0;
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else
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blink_cnt <= blink_cnt + 1'b1;
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end
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reg [2:0] border;
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reg [7:0] bitmap, attr, bitmap_next, attr_next;
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reg screen_read;
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wire attr_read = screen_read & ~hc0[0];
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wire bitmap_read = screen_read & hc0[0];
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wire [14:0] bitmap_addr = { 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] };
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wire [14:0] attr_addr = { 5'b10110, vc[7:3], hc[7:3] };
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wire [14:0] screen_addr = attr_read? attr_addr : bitmap_addr;
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wire screen_load = (vc < V_AREA) && (hc < H_AREA);
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wire screen_show = (vc < V_AREA) && (hc >= SCREEN_DELAY) && (hc < H_AREA + SCREEN_DELAY);
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wire screen_update = hc0[3:0] == 4'b1111;
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wire border_update = (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0);
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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screen_read <= 0;
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attr <= 0;
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bitmap <= 0;
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attr_next <= 0;
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bitmap_next <= 0;
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end
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else begin
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screen_read <= screen_load && (n_mreq == 1 && n_iorq == 1);
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|
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if (attr_read)
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attr_next <= vd;
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if (bitmap_read)
|
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bitmap_next <= vd;
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if (screen_load && screen_update)
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attr <= attr_next;
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else if (border_update)
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attr <= {2'b00, border, 3'b000};
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|
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if (screen_load && screen_update)
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bitmap <= bitmap_next;
|
||||
else if (hc0[0])
|
||||
bitmap <= {bitmap[6:0], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
wire pixel = bitmap[7];
|
||||
always @(posedge clk14) begin
|
||||
if (hc0[0]) begin
|
||||
if (blank)
|
||||
{i, g, r, b} = 4'b0000;
|
||||
else begin
|
||||
{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
|
||||
i = (g | r | b) & attr[6];
|
||||
end
|
||||
csync <= ~(vsync0 ^ hsync0);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/* CLOCK */
|
||||
assign clkcpu = hc[0];
|
||||
|
||||
|
||||
/* INT GENERATOR */
|
||||
localparam INT_V = 239;
|
||||
localparam INT_H_FROM = 318;
|
||||
localparam INT_H_TO = 382;
|
||||
always @(posedge clk14 or negedge rst_n) begin
|
||||
if (!rst_n)
|
||||
n_int <= 1;
|
||||
else
|
||||
n_int <= vc != INT_V || hc < INT_H_FROM || hc > INT_H_TO ;
|
||||
end
|
||||
|
||||
|
||||
/* PORT #FE */
|
||||
wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
|
||||
|
||||
wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
|
||||
reg port_fe_rd;
|
||||
always @(posedge clk14)
|
||||
port_fe_rd <= port_fe_cs && n_rd == 0;
|
||||
|
||||
reg tape_out0;
|
||||
assign tape_out = tape_in ^ tape_out0;
|
||||
always @(posedge clk14 or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
beeper <= 0;
|
||||
tape_out0 <= 0;
|
||||
border <= 0;
|
||||
end
|
||||
else if (port_fe_cs && n_wr == 0) begin
|
||||
beeper <= xd[4];
|
||||
tape_out0 <= xd[3];
|
||||
border <= xd[2:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/* PORT #7FFD */
|
||||
wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0 && xa[14] == 1;
|
||||
reg [2:0] rambank;
|
||||
reg rombank, vbank, lock_7ffd;
|
||||
always @(posedge clk14 or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
rambank <= 0;
|
||||
vbank <= 0;
|
||||
rombank <= 0;
|
||||
lock_7ffd <= 0;
|
||||
end
|
||||
else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0) begin
|
||||
rambank <= xd[2:0];
|
||||
vbank <= xd[3];
|
||||
rombank <= xd[4];
|
||||
lock_7ffd <= xd[5];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/* AY */
|
||||
always @(posedge clkcpu or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
ay_bc1 <= 0;
|
||||
ay_bdir <= 0;
|
||||
end
|
||||
else begin
|
||||
ay_bc1 <= xa[15] == 1 && xa[14] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0;
|
||||
ay_bdir <= xa[15] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0 && n_wr == 0;
|
||||
end
|
||||
end
|
||||
assign ay_clk = hc[1];
|
||||
|
||||
|
||||
/* VIDEO */
|
||||
reg [2:0] chroma0;
|
||||
chroma_gen #(.CLK_FREQ(16_000_000)) chroma_gen1(
|
||||
.cg_clock(clk16),
|
||||
.cg_rgb({g,r,b}),
|
||||
.cg_hsync(hsync1),
|
||||
.cg_enable(1'b1),
|
||||
.cg_pnsel(1'b0),
|
||||
.cg_out(chroma0)
|
||||
);
|
||||
assign chroma[0] = chroma0[1]? chroma0[0] : 1'bz;
|
||||
assign chroma[1] = chroma0[2]? chroma0[0] : 1'bz;
|
||||
|
||||
|
||||
/* MEMORY CONTROLLER */
|
||||
// 7ffe a15-14 va16-14
|
||||
// xxx 01 010 bank 2
|
||||
// xxx 10 101 bank 5
|
||||
// 000 11 000 bank 0
|
||||
// 001 11 001 bank 1 | contended
|
||||
// 010 11 010 bank 2
|
||||
// 011 11 011 bank 3 | contended
|
||||
// 100 11 100 bank 4
|
||||
// 101 11 101 bank 5 | contended (video)
|
||||
// 110 11 110 bank 6
|
||||
// 111 11 111 bank 7 | contended (video alt)
|
||||
// 7ffe a15-14 ra14
|
||||
// 0 00 0 rom0
|
||||
// 1 00 1 rom1
|
||||
|
||||
wire n_vcs_cpu = n_mreq | ~(a15 | a14);
|
||||
assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1;
|
||||
assign n_vwr = ((n_vcs_cpu == 0 && n_wr == 0) && screen_read == 0)? 1'b0 : 1'b1;
|
||||
always @(posedge clkcpu) begin
|
||||
n_romcs <= n_mreq | a15 | a14;
|
||||
end
|
||||
|
||||
assign ra14 = rombank;
|
||||
|
||||
assign va[16:0] =
|
||||
screen_read? {1'b1, vbank, screen_addr} :
|
||||
a15 & a14? {rambank, {14{1'bz}}} :
|
||||
{a14, a15, a14, {14{1'bz}}};
|
||||
|
||||
assign vd[7:0] =
|
||||
port_fe_rd? port_fe_data :
|
||||
n_iorq0 == 0 && (n_rd == 0 | n_m1 == 0)? {8{1'b1}} :
|
||||
{8{1'bz}};
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
60
cpld/zx_ula.qpf
Executable file → Normal file
60
cpld/zx_ula.qpf
Executable file → Normal file
@ -1,30 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2009 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II
|
||||
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
# Date created = 08:15:12 April 28, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "9.0"
|
||||
DATE = "08:15:12 April 28, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "zx_ula"
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2009 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II
|
||||
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
# Date created = 08:15:12 April 28, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "9.0"
|
||||
DATE = "08:15:12 April 28, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "zx_ula"
|
||||
|
||||
270
cpld/zx_ula.qsf
Executable file → Normal file
270
cpld/zx_ula.qsf
Executable file → Normal file
@ -1,136 +1,136 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2009 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II
|
||||
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
# Date created = 08:15:12 April 28, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# zx_ula_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY MAX7000S
|
||||
set_global_assignment -name DEVICE "EPM7128SLC84-15"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
|
||||
set_location_assignment PIN_10 -to b
|
||||
set_location_assignment PIN_4 -to beeper
|
||||
set_location_assignment PIN_83 -to clk14
|
||||
set_location_assignment PIN_21 -to clkcpu
|
||||
set_location_assignment PIN_5 -to g
|
||||
set_location_assignment PIN_18 -to n_int
|
||||
set_location_assignment PIN_24 -to n_iorq
|
||||
set_location_assignment PIN_22 -to n_m1
|
||||
set_location_assignment PIN_25 -to n_mreq
|
||||
set_location_assignment PIN_31 -to n_rd
|
||||
set_location_assignment PIN_20 -to n_rfsh
|
||||
set_location_assignment PIN_30 -to n_romcs
|
||||
set_location_assignment PIN_45 -to n_vrd
|
||||
set_location_assignment PIN_73 -to n_vwr
|
||||
set_location_assignment PIN_29 -to n_wr
|
||||
set_location_assignment PIN_8 -to r
|
||||
set_location_assignment PIN_1 -to rst_n
|
||||
set_location_assignment PIN_81 -to tape_out
|
||||
set_location_assignment PIN_48 -to va[16]
|
||||
set_location_assignment PIN_64 -to va[15]
|
||||
set_location_assignment PIN_61 -to va[14]
|
||||
set_location_assignment PIN_67 -to va[13]
|
||||
set_location_assignment PIN_69 -to va[12]
|
||||
set_location_assignment PIN_70 -to va[11]
|
||||
set_location_assignment PIN_75 -to va[10]
|
||||
set_location_assignment PIN_76 -to va[9]
|
||||
set_location_assignment PIN_74 -to va[8]
|
||||
set_location_assignment PIN_65 -to va[7]
|
||||
set_location_assignment PIN_77 -to va[6]
|
||||
set_location_assignment PIN_46 -to va[5]
|
||||
set_location_assignment PIN_44 -to va[4]
|
||||
set_location_assignment PIN_63 -to va[3]
|
||||
set_location_assignment PIN_68 -to va[2]
|
||||
set_location_assignment PIN_60 -to va[1]
|
||||
set_location_assignment PIN_58 -to va[0]
|
||||
set_location_assignment PIN_51 -to vd[7]
|
||||
set_location_assignment PIN_55 -to vd[6]
|
||||
set_location_assignment PIN_54 -to vd[5]
|
||||
set_location_assignment PIN_57 -to vd[4]
|
||||
set_location_assignment PIN_56 -to vd[3]
|
||||
set_location_assignment PIN_52 -to vd[2]
|
||||
set_location_assignment PIN_49 -to vd[1]
|
||||
set_location_assignment PIN_50 -to vd[0]
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
|
||||
set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
|
||||
set_location_assignment PIN_6 -to i
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
|
||||
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
|
||||
set_location_assignment PIN_28 -to a0
|
||||
set_location_assignment PIN_27 -to a1
|
||||
set_location_assignment PIN_17 -to a14
|
||||
set_location_assignment PIN_16 -to a15
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION OFF
|
||||
set_location_assignment PIN_9 -to csync
|
||||
set_location_assignment PIN_2 -to clk16
|
||||
set_location_assignment PIN_11 -to chroma[1]
|
||||
set_location_assignment PIN_12 -to chroma[0]
|
||||
set_location_assignment PIN_33 -to kd[1]
|
||||
set_location_assignment PIN_34 -to kd[0]
|
||||
set_location_assignment PIN_35 -to kd[3]
|
||||
set_location_assignment PIN_36 -to kd[2]
|
||||
set_location_assignment PIN_37 -to kd[4]
|
||||
set_location_assignment PIN_39 -to ay_bc1
|
||||
set_location_assignment PIN_40 -to ay_bdir
|
||||
set_location_assignment PIN_41 -to ay_clk
|
||||
set_location_assignment PIN_79 -to tape_in
|
||||
set_location_assignment PIN_80 -to ra14
|
||||
set_global_assignment -name FMAX_REQUIREMENT "16 MHz" -section_id clk16
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk16 -to clk16
|
||||
set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu
|
||||
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
|
||||
set_global_assignment -name SLOW_SLEW_RATE OFF
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
set_global_assignment -name SDC_FILE clocks.sdc
|
||||
set_global_assignment -name VERILOG_FILE chroma_gen.v
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2009 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II
|
||||
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
# Date created = 08:15:12 April 28, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# zx_ula_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY MAX7000S
|
||||
set_global_assignment -name DEVICE "EPM7128SLC84-15"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
|
||||
set_location_assignment PIN_10 -to b
|
||||
set_location_assignment PIN_4 -to beeper
|
||||
set_location_assignment PIN_83 -to clk14
|
||||
set_location_assignment PIN_21 -to clkcpu
|
||||
set_location_assignment PIN_5 -to g
|
||||
set_location_assignment PIN_18 -to n_int
|
||||
set_location_assignment PIN_24 -to n_iorq
|
||||
set_location_assignment PIN_22 -to n_m1
|
||||
set_location_assignment PIN_25 -to n_mreq
|
||||
set_location_assignment PIN_31 -to n_rd
|
||||
set_location_assignment PIN_20 -to n_rfsh
|
||||
set_location_assignment PIN_30 -to n_romcs
|
||||
set_location_assignment PIN_45 -to n_vrd
|
||||
set_location_assignment PIN_73 -to n_vwr
|
||||
set_location_assignment PIN_29 -to n_wr
|
||||
set_location_assignment PIN_8 -to r
|
||||
set_location_assignment PIN_1 -to rst_n
|
||||
set_location_assignment PIN_81 -to tape_out
|
||||
set_location_assignment PIN_48 -to va[16]
|
||||
set_location_assignment PIN_64 -to va[15]
|
||||
set_location_assignment PIN_61 -to va[14]
|
||||
set_location_assignment PIN_67 -to va[13]
|
||||
set_location_assignment PIN_69 -to va[12]
|
||||
set_location_assignment PIN_70 -to va[11]
|
||||
set_location_assignment PIN_75 -to va[10]
|
||||
set_location_assignment PIN_76 -to va[9]
|
||||
set_location_assignment PIN_74 -to va[8]
|
||||
set_location_assignment PIN_65 -to va[7]
|
||||
set_location_assignment PIN_77 -to va[6]
|
||||
set_location_assignment PIN_46 -to va[5]
|
||||
set_location_assignment PIN_44 -to va[4]
|
||||
set_location_assignment PIN_63 -to va[3]
|
||||
set_location_assignment PIN_68 -to va[2]
|
||||
set_location_assignment PIN_60 -to va[1]
|
||||
set_location_assignment PIN_58 -to va[0]
|
||||
set_location_assignment PIN_51 -to vd[7]
|
||||
set_location_assignment PIN_55 -to vd[6]
|
||||
set_location_assignment PIN_54 -to vd[5]
|
||||
set_location_assignment PIN_57 -to vd[4]
|
||||
set_location_assignment PIN_56 -to vd[3]
|
||||
set_location_assignment PIN_52 -to vd[2]
|
||||
set_location_assignment PIN_49 -to vd[1]
|
||||
set_location_assignment PIN_50 -to vd[0]
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
|
||||
set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
|
||||
set_location_assignment PIN_6 -to i
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
|
||||
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
|
||||
set_location_assignment PIN_28 -to a0
|
||||
set_location_assignment PIN_27 -to a1
|
||||
set_location_assignment PIN_17 -to a14
|
||||
set_location_assignment PIN_16 -to a15
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION OFF
|
||||
set_location_assignment PIN_9 -to csync
|
||||
set_location_assignment PIN_2 -to clk16
|
||||
set_location_assignment PIN_11 -to chroma[1]
|
||||
set_location_assignment PIN_12 -to chroma[0]
|
||||
set_location_assignment PIN_33 -to kd[1]
|
||||
set_location_assignment PIN_34 -to kd[0]
|
||||
set_location_assignment PIN_35 -to kd[3]
|
||||
set_location_assignment PIN_36 -to kd[2]
|
||||
set_location_assignment PIN_37 -to kd[4]
|
||||
set_location_assignment PIN_39 -to ay_bc1
|
||||
set_location_assignment PIN_40 -to ay_bdir
|
||||
set_location_assignment PIN_41 -to ay_clk
|
||||
set_location_assignment PIN_79 -to tape_in
|
||||
set_location_assignment PIN_80 -to ra14
|
||||
set_global_assignment -name FMAX_REQUIREMENT "16 MHz" -section_id clk16
|
||||
set_instance_assignment -name CLOCK_SETTINGS clk16 -to clk16
|
||||
set_global_assignment -name BASED_ON_CLOCK_SETTINGS clk14 -section_id clkcpu
|
||||
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id clkcpu
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
|
||||
set_global_assignment -name SLOW_SLEW_RATE OFF
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
set_global_assignment -name SDC_FILE clocks.sdc
|
||||
set_global_assignment -name VERILOG_FILE chroma_gen.v
|
||||
set_global_assignment -name VERILOG_FILE top.v
|
||||
Reference in New Issue
Block a user