mirror of
https://github.com/UzixLS/zx-sizif-128.git
synced 2025-07-18 23:01:28 +03:00
update firmware
1. quartus 13 may be used for build now; 2. fix small border offset; 3. fix too fast flashing with attribute bit 7.
This commit is contained in:
UzixLS
16
cpld/clocks.sdc
Normal file
16
cpld/clocks.sdc
Normal file
@ -0,0 +1,16 @@
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create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
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create_clock -period 16MHz -name {clk_16mhz} [get_ports {clk16}]
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# clkcpu 3.5
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create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk14}] [get_registers {hc0[1]}]
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# int len in turbo = 66
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create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
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# chroma carrier
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create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk16}] [get_registers {*:chroma_gen1|carrier[14]}]
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set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_16mhz}]
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set_false_path -from [get_registers {hsync1}] -to [get_clocks {chroma_carrier}]
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227
cpld/top.v
227
cpld/top.v
@ -29,8 +29,8 @@ module zx_ula(
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input [4:0] kd,
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input tape_in,
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output tape_out,
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output beeper,
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output reg tape_out,
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output reg beeper,
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output ay_clk,
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output reg ay_bdir,
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@ -44,9 +44,8 @@ module zx_ula(
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output reg csync
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);
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wire timings = 0;
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wire turbo = 0;
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wire [2:0] border;
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wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
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wire [7:0] xd = vd;
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reg n_iorq_delayed;
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always @(posedge clkcpu)
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@ -58,70 +57,25 @@ wire n_iorq0 = n_iorq | n_iorq_delayed;
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localparam H_AREA = 256;
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localparam V_AREA = 192;
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localparam SCREEN_DELAY = 8;
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localparam H_TOTAL = 448;
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localparam V_TOTAL = 320;
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localparam H_LBORDER_S48 = 32 - SCREEN_DELAY;
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localparam H_RBORDER_S48 = 64 + SCREEN_DELAY;
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localparam H_BLANK1_S48 = 16;
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localparam H_SYNC_S48 = 32;
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localparam H_BLANK2_S48 = 48;
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localparam H_TOTAL_S48 = H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48 + H_BLANK2_S48 + H_LBORDER_S48;
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localparam V_BBORDER_S48 = 56;
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localparam V_SYNC_S48 = 8;
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localparam V_TBORDER_S48 = 56;
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localparam V_TOTAL_S48 = V_AREA + V_BBORDER_S48 + V_SYNC_S48 + V_TBORDER_S48;
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reg [`CLOG2(V_TOTAL)-1:0] vc;
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reg [`CLOG2(H_TOTAL):0] hc0;
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wire [`CLOG2(H_TOTAL)-1:0] hc = hc0[$bits(hc0)-1:1];
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localparam H_LBORDER_S128 = 48 - SCREEN_DELAY;
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localparam H_RBORDER_S128 = 48 + SCREEN_DELAY;
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localparam H_BLANK1_S128 = 28;
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localparam H_SYNC_S128 = 32;
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localparam H_BLANK2_S128 = 44;
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localparam H_TOTAL_S128 = H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128 + H_LBORDER_S128;
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localparam V_BBORDER_S128 = 56;
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localparam V_SYNC_S128 = 8;
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localparam V_TBORDER_S128 = 55;
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localparam V_TOTAL_S128 = V_AREA + V_BBORDER_S128 + V_SYNC_S128 + V_TBORDER_S128;
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wire hc0_reset = hc0 == (H_TOTAL<<1) - 1'b1 ;
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wire vc_reset = vc == V_TOTAL - 1'b1 ;
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wire hsync0 = hc[8:5] == 4'b1010;
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wire vsync0 = vc[7:3] == 5'b11111;
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wire blank = (vc[7:3] == 5'b11111) || (hc[8:6] == 3'b101);
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localparam H_LBORDER_PENT = 64 - SCREEN_DELAY;
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localparam H_RBORDER_PENT = 64 + SCREEN_DELAY;
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localparam H_BLANK1_PENT = 0;
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localparam H_SYNC_PENT = 32;
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localparam H_BLANK2_PENT = 32;
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localparam H_TOTAL_PENT = H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT + H_BLANK2_PENT + H_LBORDER_PENT;
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localparam V_BBORDER_PENT = 56;
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localparam V_SYNC_PENT = 8;
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localparam V_TBORDER_PENT = 64;
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localparam V_TOTAL_PENT = V_AREA + V_BBORDER_PENT + V_SYNC_PENT + V_TBORDER_PENT;
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reg hsync1;
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always @(posedge clk14)
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hsync1 = hc[8:5] != 4'b1010;
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reg [`CLOG2(`MAX(V_TOTAL_S128, V_TOTAL_PENT))-1:0] vc;
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reg [`CLOG2(`MAX(H_TOTAL_S128, H_TOTAL_PENT)):0] hc0;
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wire [`CLOG2(`MAX(H_TOTAL_S128, H_TOTAL_PENT))-1:0] hc = hc0[$bits(hc0)-1:1];
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wire hc0_reset = timings?
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hc0 == (H_TOTAL_S128<<1) - 1'b1 :
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hc0 == (H_TOTAL_PENT<<1) - 1'b1 ;
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wire vc_reset = timings?
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vc == V_TOTAL_S128 - 1'b1 :
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vc == V_TOTAL_PENT - 1'b1 ;
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wire hsync0 = timings?
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(hc >= (H_AREA + H_RBORDER_S128 + H_BLANK1_S128)) &&
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(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128)) :
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(hc[8:5] == 4'b1010);
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wire vsync0 = timings?
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(vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128)) :
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(vc[7:3] == 5'b11111) ;
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wire blank = timings?
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((vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128))) ||
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((hc >= (H_AREA + H_RBORDER_S128)) &&
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(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128))) :
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((vc[7:3] == 5'b11111) ||
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(hc[8:6] == 3'b101));
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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hc0 <= 0;
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vc <= 0;
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end
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else if (hc0_reset) begin
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always @(posedge clk14) begin
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if (hc0_reset) begin
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hc0 <= 0;
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if (vc_reset) begin
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vc <= 0;
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@ -135,7 +89,7 @@ always @(posedge clk14 or negedge rst_n) begin
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end
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end
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reg [3:0] blink_cnt;
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reg [4:0] blink_cnt;
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wire blink = blink_cnt[$bits(blink_cnt)-1];
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always @(posedge n_int or negedge rst_n) begin
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if (!rst_n)
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@ -144,20 +98,8 @@ always @(posedge n_int or negedge rst_n) begin
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blink_cnt <= blink_cnt + 1'b1;
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end
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reg [2:0] border;
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reg [7:0] bitmap, attr, bitmap_next, attr_next;
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wire pixel = bitmap[7];
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always @(posedge clk14) begin
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if (hc0[0]) begin
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if (blank)
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{i, g, r, b} = 4'b0000;
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else begin
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{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
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i = (g | r | b) & attr[6];
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end
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csync <= ~(vsync0 ^ hsync0);
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end
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end
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reg screen_read;
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wire attr_read = screen_read & ~hc0[0];
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wire bitmap_read = screen_read & hc0[0];
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@ -167,8 +109,7 @@ wire [14:0] screen_addr = attr_read? attr_addr : bitmap_addr;
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wire screen_load = (vc < V_AREA) && (hc < H_AREA);
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wire screen_show = (vc < V_AREA) && (hc >= SCREEN_DELAY) && (hc < H_AREA + SCREEN_DELAY);
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wire screen_update = hc0[3:0] == 4'b1111;
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wire border_update = ((screen_load == 0 && screen_show == 0) || (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0 && timings == 0))
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&& (timings == 0 || hc0[3:0] == 4'b1111);
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wire border_update = (screen_load == 0 && hc0[3:0] == 4'b1111) || (screen_show == 0);
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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@ -198,66 +139,76 @@ always @(posedge clk14 or negedge rst_n) begin
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end
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end
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wire [15:0] xa = {a15, a14, va[13:2], a1, a0};
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/* PORT #FE */
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wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
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reg port_fe_rd;
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always @(posedge clk14)
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port_fe_rd <= port_fe_cs && n_rd == 0;
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wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
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reg [7:0] port_fe;
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assign beeper = port_fe[4];
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assign tape_out = port_fe[3] ^ tape_in;
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assign border = port_fe[2:0];
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n)
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port_fe <= 0;
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else if (port_fe_cs && n_wr == 0)
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port_fe <= vd;
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end
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/* PORT #7FFD */
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wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0;
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reg [7:0] port_7ffd;
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wire [2:0] rambank = port_7ffd[2:0];
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wire vbank = port_7ffd[3];
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wire rombank = port_7ffd[4];
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wire lock_7ffd = port_7ffd[5];
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n)
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port_7ffd <= 0;
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else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0)
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port_7ffd <= vd;
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end
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/* INT GENERATOR */
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localparam INT_V_S48 = 248;
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localparam INT_H_FROM_S48 = 0;
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localparam INT_H_TO_S48 = 63;
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localparam INT_V_S128 = 248;
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localparam INT_H_FROM_S128 = 2;
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localparam INT_H_TO_S128 = 65;
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localparam INT_V_PENT = 239;
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localparam INT_H_FROM_PENT = 320;
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localparam INT_H_TO_PENT = 384;
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wire pixel = bitmap[7];
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always @(posedge clk14) begin
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n_int <= timings?
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(vc != INT_V_S128 || hc < INT_H_FROM_S128 || hc > INT_H_TO_S128) :
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(vc != INT_V_PENT || hc < INT_H_FROM_PENT || hc > INT_H_TO_PENT) ;
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if (hc0[0]) begin
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if (blank)
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{i, g, r, b} = 4'b0000;
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else begin
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{g, r, b} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
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i = (g | r | b) & attr[6];
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end
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csync <= ~(vsync0 ^ hsync0);
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end
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end
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/* CLOCK */
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reg [2:0] clk_cnt;
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always @(posedge clk14) begin
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clk_cnt <= clk_cnt + 1'b1;
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assign clkcpu = hc[0];
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/* INT GENERATOR */
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localparam INT_V = 239;
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localparam INT_H_FROM = 318;
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localparam INT_H_TO = 382;
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n)
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n_int <= 1;
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else
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n_int <= vc != INT_V || hc < INT_H_FROM || hc > INT_H_TO ;
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end
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/* PORT #FE */
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wire port_fe_cs = n_m1 == 1 && n_iorq0 == 0 && xa[0] == 0;
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wire [7:0] port_fe_data = {1'b1, tape_in, 1'b1, kd[4:0]};
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reg port_fe_rd;
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always @(posedge clk14)
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port_fe_rd <= port_fe_cs && n_rd == 0;
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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beeper <= 0;
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tape_out <= 0;
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border <= 0;
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end
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else if (port_fe_cs && n_wr == 0) begin
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beeper <= xd[4];
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tape_out <= xd[3];
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border <= xd[2:0];
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end
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end
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/* PORT #7FFD */
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wire port_7ffd_cs = n_m1 == 1 && n_iorq0 == 0 && xa[1] == 0 && xa[15] == 0 && xa[14] == 1;
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reg [2:0] rambank;
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reg rombank, vbank, lock_7ffd;
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always @(posedge clk14 or negedge rst_n) begin
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if (!rst_n) begin
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rambank <= 0;
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vbank <= 0;
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rombank <= 0;
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lock_7ffd <= 0;
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end
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else if (port_7ffd_cs && n_wr == 0 && lock_7ffd == 0) begin
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rambank <= xd[2:0];
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vbank <= xd[3];
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rombank <= xd[4];
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lock_7ffd <= xd[5];
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end
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end
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assign clkcpu = turbo? clk_cnt[0] : clk_cnt[1];
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/* AY */
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@ -271,7 +222,7 @@ always @(posedge clkcpu or negedge rst_n) begin
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ay_bdir <= xa[15] == 1 && xa[1] == 0 && n_m1 == 1 && n_iorq0 == 0 && n_wr == 0;
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end
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end
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assign ay_clk = clk_cnt[2];
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assign ay_clk = hc[1];
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/* VIDEO */
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@ -279,7 +230,7 @@ reg [2:0] chroma0;
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chroma_gen chroma_gen1(
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.cg_clock(clk16),
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.cg_rgb({g,r,b}),
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.cg_hsync(~hsync0),
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.cg_hsync(hsync1),
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.cg_enable(1'b1),
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.cg_pnsel(1'b0),
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.cg_out(chroma0)
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@ -305,7 +256,7 @@ assign chroma[1] = chroma0[2]? chroma0[0] : 1'bz;
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// 1 00 1 rom1
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wire n_vcs_cpu = n_mreq | ~(a15 | a14);
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assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1 ;
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assign n_vrd = ((n_vcs_cpu == 0 && n_rd == 0) || screen_read == 1)? 1'b0 : 1'b1;
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assign n_vwr = ((n_vcs_cpu == 0 && n_wr == 0) && screen_read == 0)? 1'b0 : 1'b1;
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always @(posedge clkcpu) begin
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n_romcs <= n_mreq | a15 | a14;
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE "EPM7128SLC84-15"
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set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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@ -92,7 +92,7 @@ set_location_assignment PIN_49 -to vd[1]
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set_location_assignment PIN_50 -to vd[0]
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name FMAX_REQUIREMENT "14 MHz"
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set_global_assignment -name FMAX_REQUIREMENT "14 MHz" -section_id clk14
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set_location_assignment PIN_6 -to i
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@ -130,6 +130,8 @@ set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
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set_global_assignment -name SLOW_SLEW_RATE OFF
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name VHDL_FILE chroma_gen16.vhd
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set_global_assignment -name VERILOG_FILE top.v
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set_global_assignment -name VERILOG_INCLUDE_FILE util.vh
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