mirror of
https://github.com/UzixLS/zx-multisound.git
synced 2025-07-19 07:11:47 +03:00
105 lines
2.1 KiB
Verilog
105 lines
2.1 KiB
Verilog
`timescale 1ns/1ps
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module testbench_top();
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reg rst_n;
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reg clk32;
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/* TOP ENTRY */
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// zx_multisound zx_multisound0(
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// .rst_n(rst_n),
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// .clk32(clk32),
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// .cfg(5'b11111),
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// .a(16'hFFFF),
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// // .d(8'hFF),
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// .n_rd(1'b1),
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// .n_wr(1'b1),
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// .n_iorq(1'b1),
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// .n_mreq(1'b1),
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// .n_m1(1'b1),
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// .ga(16'hFFFF),
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// // .gd(8'hFF),
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// .n_grd(1'b1),
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// .n_gwr(1'b1),
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// .n_gm1(1'b1),
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// .n_gmreq(1'b1),
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// .n_giorq(1'b1)
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// );
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/* CLOCKS & RESET */
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initial begin
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rst_n = 0;
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#50 rst_n = 1;
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end
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always begin
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clk32 = 0;
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#15.625 clk32 = 1;
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#15.625;
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end
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wire [15:0] sine_vol;
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sine_dds sine_dds_vol(clk32, ~rst_n, 256, sine_vol);
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wire [15:0] sine_dac;
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sine_dds sine_dds_dac(clk32, ~rst_n, 1024, sine_dac);
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// wire [5:0] volx = 6'h00;
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// wire [5:0] volx = 6'h1F;
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wire [5:0] volx = 6'h3F;
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// wire [5:0] volx = sine_vol[15:10];
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// reg [5:0] volx = 6'h3F;
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// initial begin
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// #2_000_000 volx = 0;
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// #2_000_000 volx = 6'h1F;
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// #2_000_000 volx = 0;
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// #2_000_000 volx = 6'h3F;
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// end
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// wire [7:0] dacx = 8'h00;
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// wire [7:0] dacx = 8'h80;
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// wire [7:0] dacx = 8'hFF;
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wire [7:0] dacx = sine_vol[15:8];
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wire [7:0] dacx0 = dacx[7]? {~dacx[7],dacx[6:0]} : {dacx[7],~dacx[6:0]};
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reg [5:0] volx_cnt;
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reg [7:0] dacx_cnt;
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wire volx_en = (volx_cnt < volx) || (&volx);
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wire dacx_cnt7 = dacx_cnt[7];
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wire dacx7 = dacx[7];
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wire dacx_out = dacx_cnt[7]? dacx[7] : clk32;
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always @(negedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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volx_cnt <= 0;
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dacx_cnt <= 0;
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end
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else begin
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volx_cnt <= volx_cnt + 6'd31;
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if (volx_en)
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dacx_cnt <= dacx_cnt[6:0] + dacx0[6:0];
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else
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dacx_cnt[7] <= 0;
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end
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end
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/* TESTBENCH CONTROL */
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integer fhandle;
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initial begin
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fhandle = $fopen("testbench_pwl.txt","w");
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$timeformat(0, 10, "", 0);
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$dumpfile("testbench.vcd");
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$dumpvars;
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#10_000_000;
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$fclose(fhandle);
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$finish;
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end
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`define SCALE 3.3
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always @(negedge clk32 or posedge clk32) begin
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$fwrite(fhandle, "%t %f\n", $time, dacx_out*`SCALE);
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end
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endmodule
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