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44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
module sine_dds(
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input clk ,
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input reset,
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input [23:0] fcw,
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output [15:0] dds_sin,
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output dds_clk,
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output dds_stb
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);
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reg [15:0] rom_memory [1023:0];
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initial begin
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$readmemh("sine.mem", rom_memory);
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end
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reg [23:0] accu;
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reg [1:0] fdiv_cnt;
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wire accu_en;
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reg accu_msb_q;
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wire [9:0] lut_index;
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//process for frequency divider
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always @(posedge clk)
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begin
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if(reset == 1'b1)
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fdiv_cnt <= 0; //synchronous reset
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else if(accu_en == 1'b1)
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fdiv_cnt <= 0;
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else
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fdiv_cnt <= fdiv_cnt +1;
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end
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//logic for accu enable signal, resets also the frequency divider counter
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assign accu_en = (fdiv_cnt == 2'd2) ? 1'b1 : 1'b0;
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//process for phase accumulator
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always @(posedge clk)
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begin
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if(reset == 1'b1)
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accu <= 0; //synchronous reset
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else if(accu_en == 1'b1)
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accu <= accu + fcw;
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end
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//10 msb's of the phase accumulator are used to index the sinewave lookup-table
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assign lut_index = accu[23:14];
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//16-bit sine value from lookup table
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assign dds_sin = rom_memory[lut_index];
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endmodule
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