add testbench

cpld/tb/Makefile

@@ -0,0 +1,31 @@
+export PATH:=/opt/modelsim201/modelsim_ase/bin:/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH}
+
+all: testbench_top
+
+testbench_top: IVFLAGS+=-I../rtl/
+testbench_top: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017 +nowarn3155
+testbench_top: testbench_top.v sine_dds.v
+
+xtestbench_%:
+	iverilog -g2005-sv ${IVFLAGS} -o $@.vvp $^
+	vvp $@.vvp
+	@rm $@.vvp
+
+testbench_%:
+	test ! -d work || rm -rf work
+	vlib work
+	test ! -n "$(filter %.v %.sv,$^)" || vlog -quiet -sv ${VLOGFLAGS} $(filter %.v %sv,$^)
+	test ! -n "$(filter %.vhd %.vhdl,$^)" || vcom -quiet ${VCOMFLAGS} $(filter %.vhd %.vhdl,$^)
+	vsim ${VSIMFLAGS} -batch -quiet -do 'run -all' $@
+	test ! -r transcript || rm transcript
+
+%.bin: %.asm
+	sjasmplus $<
+
+%.mem: %.bin
+	srec_cat $< -binary -o $@ -vmem 8
+
+clean:
+	rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
+
+-include Makefile.local

cpld/tb/circuit.asc

@@ -0,0 +1,40 @@
+Version 4
+SHEET 1 880 680
+WIRE 48 176 48 160
+WIRE 96 176 48 176
+WIRE 224 176 224 160
+WIRE 224 176 176 176
+WIRE 288 176 224 176
+WIRE 432 176 432 160
+WIRE 432 176 352 176
+WIRE 224 192 224 176
+FLAG 48 256 0
+FLAG 224 256 0
+FLAG 432 256 0
+FLAG 432 160 Out
+FLAG 48 160 In
+FLAG 224 160 Mid
+SYMBOL res 80 192 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R6
+SYMATTR Value 1k
+SYMBOL voltage 48 160 R0
+WINDOW 0 -45 35 Bottom 2
+WINDOW 3 -95 81 Top 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V5
+SYMATTR Value PWL file=testbench_pwl.txt
+SYMBOL cap 208 192 R0
+SYMATTR InstName C1
+SYMATTR Value 10n
+SYMBOL res 416 160 R0
+SYMATTR InstName R1
+SYMATTR Value 100k
+SYMBOL cap 352 160 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C2
+SYMATTR Value 1n
+TEXT -24 112 Left 2 !.tran 10m

cpld/tb/sine.mem

@@ -0,0 +1 @@
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cpld/tb/sine_dds.v

@@ -0,0 +1,43 @@
+module sine_dds(
+        input clk ,
+        input reset,
+        input [23:0] fcw,
+        output [15:0] dds_sin,
+        output dds_clk,
+        output dds_stb
+            );
+reg [15:0] rom_memory [1023:0];
+initial begin
+    $readmemh("sine.mem", rom_memory);
+end
+   reg [23:0] accu;
+   reg [1:0] fdiv_cnt;
+   wire accu_en;
+   reg accu_msb_q;
+   wire [9:0] lut_index;
+
+//process for frequency divider
+always @(posedge clk)
+begin
+      if(reset == 1'b1)
+         fdiv_cnt <= 0; //synchronous reset
+      else if(accu_en == 1'b1)
+         fdiv_cnt <= 0;
+      else
+         fdiv_cnt <= fdiv_cnt +1;
+end
+//logic for accu enable signal, resets also the frequency divider counter
+assign accu_en = (fdiv_cnt == 2'd2) ? 1'b1 : 1'b0;
+//process for phase accumulator
+always @(posedge clk)
+begin
+      if(reset == 1'b1)
+                accu <= 0; //synchronous reset
+      else if(accu_en == 1'b1)
+            accu <= accu + fcw;
+end
+//10 msb's of the phase accumulator are used to index the sinewave lookup-table
+assign lut_index = accu[23:14];
+//16-bit sine value from lookup table
+assign dds_sin = rom_memory[lut_index];
+endmodule

cpld/tb/testbench_top.v

@@ -0,0 +1,104 @@
+`timescale 1ns/1ps
+module testbench_top();
+
+reg rst_n;
+reg clk32;
+
+/* TOP ENTRY */
+// zx_multisound zx_multisound0(
+//     .rst_n(rst_n),
+//     .clk32(clk32),
+//     .cfg(5'b11111),
+//     .a(16'hFFFF),
+//     // .d(8'hFF),
+//     .n_rd(1'b1),
+//     .n_wr(1'b1),
+//     .n_iorq(1'b1),
+//     .n_mreq(1'b1),
+//     .n_m1(1'b1),
+//     .ga(16'hFFFF),
+//     // .gd(8'hFF),
+//     .n_grd(1'b1),
+//     .n_gwr(1'b1),
+//     .n_gm1(1'b1),
+//     .n_gmreq(1'b1),
+//     .n_giorq(1'b1)
+// );
+
+/* CLOCKS & RESET */
+initial begin
+    rst_n = 0;
+    #50 rst_n = 1;
+end
+
+always begin
+    clk32 = 0;
+    #15.625 clk32 = 1;
+    #15.625;
+end
+
+
+wire [15:0] sine_vol;
+sine_dds sine_dds_vol(clk32, ~rst_n, 256, sine_vol);
+wire [15:0] sine_dac;
+sine_dds sine_dds_dac(clk32, ~rst_n, 1024, sine_dac);
+
+// wire [5:0] volx = 6'h00;
+// wire [5:0] volx = 6'h1F;
+wire [5:0] volx = 6'h3F;
+// wire [5:0] volx = sine_vol[15:10];
+// reg [5:0] volx = 6'h3F;
+// initial begin
+//     #2_000_000 volx = 0;
+//     #2_000_000 volx = 6'h1F;
+//     #2_000_000 volx = 0;
+//     #2_000_000 volx = 6'h3F;
+// end
+
+// wire [7:0] dacx = 8'h00;
+// wire [7:0] dacx = 8'h80;
+// wire [7:0] dacx = 8'hFF;
+wire [7:0] dacx = sine_vol[15:8];
+
+
+wire [7:0] dacx0 = dacx[7]? {~dacx[7],dacx[6:0]} : {dacx[7],~dacx[6:0]};
+reg [5:0] volx_cnt;
+reg [7:0] dacx_cnt;
+wire volx_en = (volx_cnt < volx) || (&volx);
+wire dacx_cnt7 = dacx_cnt[7];
+wire dacx7 = dacx[7];
+wire dacx_out = dacx_cnt[7]? dacx[7] : clk32;
+always @(negedge clk32 or negedge rst_n) begin
+    if (!rst_n) begin
+       volx_cnt <= 0;
+       dacx_cnt <= 0;
+    end
+    else begin
+        volx_cnt <= volx_cnt + 6'd31;
+        if (volx_en)
+            dacx_cnt <= dacx_cnt[6:0] + dacx0[6:0];
+        else
+            dacx_cnt[7] <= 0;
+    end
+end
+
+
+
+/* TESTBENCH CONTROL */
+integer fhandle;
+initial begin
+    fhandle = $fopen("testbench_pwl.txt","w");
+    $timeformat(0, 10, "", 0);
+    $dumpfile("testbench.vcd");
+    $dumpvars;
+    #10_000_000;
+    $fclose(fhandle);
+    $finish;
+end
+
+`define SCALE 3.3
+always @(negedge clk32 or posedge clk32) begin
+    $fwrite(fhandle, "%t %f\n", $time, dacx_out*`SCALE);
+end
+
+endmodule