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https://github.com/UzixLS/zx-multisound.git
synced 2025-07-18 23:01:31 +03:00
fix compatibility with NemoIDE
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@ -105,9 +105,9 @@ wire clk16 = clk8_cnt[0];
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/* TURBO SOUND FM */
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wire port_bffd = a[15:14] == 2'b10 && a[1:0] == 2'b01 && ym_ena;
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wire port_fffd = a[15:14] == 2'b11 && a[1:0] == 2'b01 && ym_ena;
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wire port_fffd_full = a[15:13] == 3'b111 && a[1:0] == 2'b01 && ym_ena; // required for compatibility with #dffd port
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wire port_bffd = a[15:14] == 2'b10 && a[3:0] == 4'b1101 && ym_ena;
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wire port_fffd = a[15:14] == 2'b11 && a[3:0] == 4'b1101 && ym_ena;
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wire port_fffd_full = a[15:13] == 3'b111 && a[3:0] == 4'b1101 && ym_ena; // required for compatibility with #dffd port
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reg ym_chip_sel, ym_get_stat;
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wire ym_a0 = (~n_rd & a[14] & ~ym_get_stat) | (~n_wr & ~a[14]);
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assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd));
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@ -136,7 +136,7 @@ wire port_ff = a[7:0] == 8'hFF && saa_ena && !rom_m1_access;
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assign n_saa_cs = ~(port_ff && ioreq_wr);
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wire saa_a0 = a[8];
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wire port_fffd_saa = a[15:14] == 2'b11 && a[1:0] == 2'b01 && saa_ena;
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wire port_fffd_saa = a[15:14] == 2'b11 && a[3:0] == 4'b1101 && saa_ena;
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reg saa_clk_en;
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n)
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out/cpld.rev.A1.pof
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out/cpld.rev.A1.pof
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