mirror of
https://github.com/UzixLS/zx-multisound.git
synced 2025-07-18 23:01:31 +03:00
add cpld sources
This commit is contained in:
Eugene Lozovoy
287
cpld/rtl/top.v
Normal file
287
cpld/rtl/top.v
Normal file
@ -0,0 +1,287 @@
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module zx_multisound(
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input rst_n,
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input clk32,
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input clkx,
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input [2:0] cfg,
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input [15:0] a,
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inout [7:0] d,
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input n_rd,
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input n_wr,
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input n_iorq,
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input n_m1,
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output n_wait,
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output n_iorqge,
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input dos,
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input iodos,
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output aa0,
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inout [7:0] ad,
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output n_ard,
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output n_awr,
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output ym_m,
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output n_ym1_cs,
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output n_ym2_cs,
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output reg fm1_ena,
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output reg fm2_ena,
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output n_saa_cs,
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output saa_clk,
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output midi_clk,
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input [15:0] ga,
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inout [7:0] gd,
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output n_grst,
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output gclk,
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output reg n_gint,
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input n_grd,
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input n_gwr,
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input n_gm1,
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input n_gmreq,
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input n_giorq,
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output n_grom,
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output n_gram,
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output [18:15] gma,
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output gdac0,
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output gdac1,
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output gdac2,
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output gdac3
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);
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wire n_iorq0 = n_iorq | ~dos | ~iodos;
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/* CONFIGURATION */
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wire ym_ena = cfg[0];
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wire saa_ena = cfg[1];
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wire gs_ena = cfg[2];
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/* TURBO SOUND FM */
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wire port_bffd = a[15:14] == 2'b10 && a[1:0] == 2'b01 && ym_ena;
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wire port_fffd = a[15:14] == 2'b11 && a[1:0] == 2'b01 && ym_ena;
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wire port_fffd_full = a[15:13] == 3'b111 && a[1:0] == 2'b01 && ym_ena; // required for compatibility with #dffd port
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reg ym_chip_sel, ym_get_stat;
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wire ym_a0 = (~n_rd & a[14] & ~ym_get_stat) | (~n_wr & ~a[14]);
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assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq0 && n_m1);
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assign n_ym2_cs = ~( ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq0 && n_m1);
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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ym_chip_sel <= 0;
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ym_get_stat <= 0;
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fm1_ena <= 0;
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fm2_ena <= 0;
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end
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else if (port_fffd && ~n_iorq0 && ~n_wr && d[7:3] == 5'b11111) begin
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ym_chip_sel <= ~d[0];
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ym_get_stat <= ~d[1];
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fm1_ena <= d[2]? 1'b0 : 1'bz;
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fm2_ena <= d[2]? 1'b0 : 1'bz;
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end
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end
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reg [5:0] ym_m_cnt = 0;
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assign ym_m = ym_m_cnt[5];
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always @(posedge clk32) begin
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ym_m_cnt <= ym_m_cnt + 6'd7;
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end
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/* SAA1099 */
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wire port_ff = a[7:0] == 8'hFF && saa_ena;
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assign n_saa_cs = ~(port_ff && ~n_iorq0 && ~n_wr);
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wire saa_a0 = a[8];
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reg saa_clk_en;
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always @(posedge clk32) begin
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if (!rst_n)
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saa_clk_en <= 1'b0;
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else if (~n_saa_cs && ~n_awr)
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saa_clk_en <= 1'b1;
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end
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reg [1:0] saa_clk_cnt = 0;
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assign saa_clk = saa_clk_en? saa_clk_cnt[1] : 1'b0;
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always @(posedge clk32) begin
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saa_clk_cnt <= saa_clk_cnt + 1'b1;
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end
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/* MIDI */
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reg [2:0] midi_clk_cnt = 0;
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assign midi_clk = midi_clk_cnt[2];
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always @(posedge clk32) begin
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midi_clk_cnt <= midi_clk_cnt + 3'd3;
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end
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/* GENERAL SOUND */
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assign gclk = midi_clk;
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assign n_grst = rst_n;
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reg [8:0] g_int_cnt;
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wire g_int_reload = g_int_cnt[8:6] == 4'b101;
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always @(posedge gclk or negedge rst_n) begin
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if (!rst_n) begin
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g_int_cnt <= 0;
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n_gint <= 1'b1;
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end
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else begin
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if (g_int_reload)
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g_int_cnt <= 0;
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else
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g_int_cnt <= g_int_cnt + 1'b1;
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if (g_int_reload)
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n_gint <= 1'b0;
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else if (g_int_cnt[5])
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n_gint <= 1'b1;
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end
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end
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/* GS EXTERNAL REGISTERS */
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reg [7:0] gs_regb3, gs_regbb;
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wire port_b3 = a[7:0] == 8'hB3 && gs_ena;
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wire port_bb = a[7:0] == 8'hBB && gs_ena;
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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gs_regb3 <= 0;
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gs_regbb <= 0;
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end
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else begin
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if (port_b3 && ~n_iorq0 && ~n_wr)
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gs_regb3 <= d;
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if (port_bb && ~n_iorq0 && ~n_wr)
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gs_regbb <= d;
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end
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end
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/* GS INTERNAL REGISTERS */
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reg [7:0] gs_reg00, gs_reg03;
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wire [3:0] gs_page = gs_reg00[3:0];
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reg [5:0] gs_vol0, gs_vol1, gs_vol2, gs_vol3;
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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gs_reg00 <= 0;
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gs_reg03 <= 0;
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gs_vol0 <= 0;
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gs_vol1 <= 0;
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gs_vol2 <= 0;
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gs_vol3 <= 0;
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end
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else if (~n_giorq && ~n_gwr) begin
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if (ga[3:0] == 4'h0) gs_reg00 <= gd;
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if (ga[3:0] == 4'h3) gs_reg03 <= gd;
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if (ga[3:0] == 4'h6) gs_vol0 <= gd[5:0];
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if (ga[3:0] == 4'h7) gs_vol1 <= gd[5:0];
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if (ga[3:0] == 4'h8) gs_vol2 <= gd[5:0];
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if (ga[3:0] == 4'h9) gs_vol3 <= gd[5:0];
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end
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end
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reg [7:0] gs_dac0, gs_dac1, gs_dac2, gs_dac3;
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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gs_dac0 <= 0;
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gs_dac1 <= 0;
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gs_dac2 <= 0;
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gs_dac3 <= 0;
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end
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else if (~n_gmreq && ~n_grd && ga[15:13] == 3'b011) begin
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if (ga[9:8] == 2'b00) gs_dac0 <= gd;
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if (ga[9:8] == 2'b01) gs_dac1 <= gd;
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if (ga[9:8] == 2'b10) gs_dac2 <= gd;
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if (ga[9:8] == 2'b11) gs_dac3 <= gd;
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end
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end
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/* GS STATUS REGISTER */
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reg gs_status0, gs_status7;
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wire [7:0] gs_status = {gs_status7, 6'b111111, gs_status0};
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always @(posedge clk32) begin
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if ((~n_giorq && n_gm1 && ga[3:0] == 4'h2) || (~n_iorq0 && ~n_rd && port_b3))
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gs_status7 <= 1'b0;
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else if ((~n_giorq && n_gm1 && ga[3:0] == 4'h3) || (~n_iorq0 && ~n_wr && port_b3))
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gs_status7 <= 1'b1;
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else if (~n_giorq && n_gm1 && ga[3:0] == 4'hA)
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gs_status7 <= ~gs_reg00[0];
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end
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always @(posedge clk32) begin
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if (~n_giorq && n_gm1 && ga[3:0] == 4'h5)
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gs_status0 <= 1'b0;
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else if (~n_iorq0 && ~n_wr && port_bb)
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gs_status0 <= 1'b1;
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else if (~n_giorq && n_gm1 && ga[3:0] == 4'hB)
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gs_status0 <= gs_vol0[5];
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end
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/* GS DAC */
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reg vol0_en, vol1_en, vol2_en, vol3_en;
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reg [5:0] vol_cnt;
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reg [8:0] dac0_cnt, dac1_cnt, dac2_cnt, dac3_cnt;
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assign gdac0 = dac0_cnt[8];
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assign gdac1 = dac1_cnt[8];
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assign gdac2 = dac2_cnt[8];
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assign gdac3 = dac3_cnt[8];
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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{vol0_en, vol1_en, vol2_en, vol3_en} <= 0;
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vol_cnt <= 0;
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dac0_cnt <= 0;
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dac1_cnt <= 0;
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dac2_cnt <= 0;
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dac3_cnt <= 0;
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end
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else begin
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vol_cnt <= vol_cnt + 6'd31;
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vol0_en <= vol_cnt < gs_vol0;
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vol1_en <= vol_cnt < gs_vol1;
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vol2_en <= vol_cnt < gs_vol2;
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vol3_en <= vol_cnt < gs_vol3;
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if (vol0_en) dac0_cnt <= dac0_cnt[7:0] + gs_dac0; else dac0_cnt[8] <= 0;
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if (vol1_en) dac1_cnt <= dac1_cnt[7:0] + gs_dac1; else dac1_cnt[8] <= 0;
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if (vol2_en) dac2_cnt <= dac2_cnt[7:0] + gs_dac2; else dac2_cnt[8] <= 0;
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if (vol3_en) dac3_cnt <= dac3_cnt[7:0] + gs_dac3; else dac3_cnt[8] <= 0;
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end
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end
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/* GS BUS CONTROLLER */
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assign n_grom = (~n_gmreq && ((ga[15:14] == 2'b00) || (ga[15] == 1'b1 && gs_page == 0)))? 1'b0 : 1'b1;
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assign n_gram = (~n_gmreq && n_grom)? 1'b0 : 1'b1;
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assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page;
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assign gd =
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(~n_giorq && ~n_grd && ga[3:0] == 4'h4)? gs_status :
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(~n_giorq && ~n_grd && ga[3:0] == 4'h2)? gs_regb3 :
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(~n_giorq && ~n_grd && ga[3:0] == 4'h1)? gs_regbb :
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(~n_giorq && (~n_grd || ~n_gm1))? {8{1'b1}} :
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{8{1'bz}} ;
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/* BUS CONTROLLER */
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assign n_ard = n_rd | n_iorq0;
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assign n_awr = n_wr | n_iorq0;
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assign aa0 = n_iorq? aa0 : a[1]? saa_a0 : ym_a0 ;
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assign ad =
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~n_awr && ~n_iorq0 && (port_fffd || port_bffd || port_ff)? d :
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8'bzzzzzzzz;
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assign n_wait = 1'bz;
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assign n_iorqge = (n_m1 && (port_fffd_full || port_bffd || port_b3 || port_bb))? 1'b1 : 1'bz;
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assign d =
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~n_rd && ~n_iorq0 && port_fffd_full? ad :
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~n_rd && ~n_iorq0 && port_b3? gs_reg03 :
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~n_rd && ~n_iorq0 && port_bb? gs_status :
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8'bzzzzzzzz;
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endmodule
|
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19
cpld/syn/Makefile
Normal file
19
cpld/syn/Makefile
Normal file
@ -0,0 +1,19 @@
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REVISION = zx_multisound
|
||||
|
||||
.PHONY: build program clean
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||||
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build:
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quartus_sh --no_banner --flow compile zx_multisound -c ${REVISION}
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||||
|
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program:
|
||||
quartus_pgm --no_banner --mode=jtag -o "BVP;output/${REVISION}.pof"
|
||||
|
||||
clean:
|
||||
rm -rf db incremental_db output
|
||||
|
||||
report:
|
||||
cat output/${REVISION}.*.smsg output/${REVISION}.cmp.rpt |grep -e Error -e Critical -e Warning |grep -v -e "Family doesn't support jitter analysis" -e "Force Fitter to Avoid Periphery Placement Warnings"
|
||||
|
||||
export PATH:=/opt/quartus13.0sp1/quartus/bin:/cygdrive/c/Hwdev/quartus130sp1/quartus/bin:${PATH}
|
||||
|
||||
-include Makefile.local
|
||||
3
cpld/syn/clocks.sdc
Normal file
3
cpld/syn/clocks.sdc
Normal file
@ -0,0 +1,3 @@
|
||||
create_clock -period 32.1MHz -name {clk_32mhz} [get_ports {clk32}]
|
||||
|
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create_generated_clock -name {gclk} -divide_by 2 -source [get_ports {clk32}] [get_registers {midi_clk_cnt[2]}]
|
||||
30
cpld/syn/zx_multisound.qpf
Normal file
30
cpld/syn/zx_multisound.qpf
Normal file
@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 12:04:27 October 04, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "12:04:27 October 04, 2020"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "zx_multisound"
|
||||
160
cpld/syn/zx_multisound.qsf
Normal file
160
cpld/syn/zx_multisound.qsf
Normal file
@ -0,0 +1,160 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 12:04:27 October 04, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# zx_multisound_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY MAX3000A
|
||||
set_global_assignment -name DEVICE "EPM3256ATC144-10"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY zx_multisound
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:04:27 OCTOBER 04, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name SDC_FILE clocks.sdc
|
||||
set_global_assignment -name VERILOG_FILE ../rtl/top.v
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
set_location_assignment PIN_2 -to d[2]
|
||||
set_location_assignment PIN_7 -to ad[1]
|
||||
set_location_assignment PIN_8 -to ad[2]
|
||||
set_location_assignment PIN_9 -to ad[3]
|
||||
set_location_assignment PIN_10 -to ad[4]
|
||||
set_location_assignment PIN_11 -to ad[5]
|
||||
set_location_assignment PIN_12 -to ad[6]
|
||||
set_location_assignment PIN_14 -to ad[7]
|
||||
set_location_assignment PIN_15 -to n_saa_cs
|
||||
set_location_assignment PIN_16 -to saa_clk
|
||||
set_location_assignment PIN_19 -to n_ym2_cs
|
||||
set_location_assignment PIN_18 -to n_ym1_cs
|
||||
set_location_assignment PIN_21 -to n_awr
|
||||
set_location_assignment PIN_22 -to n_ard
|
||||
set_location_assignment PIN_23 -to aa0
|
||||
set_location_assignment PIN_25 -to ym_m
|
||||
set_location_assignment PIN_27 -to ad[0]
|
||||
set_location_assignment PIN_28 -to fm2_ena
|
||||
set_location_assignment PIN_29 -to fm1_ena
|
||||
set_location_assignment PIN_35 -to midi_clk
|
||||
set_location_assignment PIN_36 -to gdac3
|
||||
set_location_assignment PIN_37 -to gdac2
|
||||
set_location_assignment PIN_38 -to gdac1
|
||||
set_location_assignment PIN_39 -to gdac0
|
||||
set_location_assignment PIN_40 -to ga[11]
|
||||
set_location_assignment PIN_41 -to gclk
|
||||
set_location_assignment PIN_67 -to ga[1]
|
||||
set_location_assignment PIN_42 -to ga[12]
|
||||
set_location_assignment PIN_43 -to ga[13]
|
||||
set_location_assignment PIN_44 -to ga[14]
|
||||
set_location_assignment PIN_45 -to ga[15]
|
||||
set_location_assignment PIN_46 -to ga[10]
|
||||
set_location_assignment PIN_47 -to ga[9]
|
||||
set_location_assignment PIN_48 -to ga[8]
|
||||
set_location_assignment PIN_49 -to n_gint
|
||||
set_location_assignment PIN_53 -to ga[7]
|
||||
set_location_assignment PIN_54 -to n_gmreq
|
||||
set_location_assignment PIN_55 -to ga[6]
|
||||
set_location_assignment PIN_56 -to n_giorq
|
||||
set_location_assignment PIN_60 -to ga[5]
|
||||
set_location_assignment PIN_61 -to n_grst
|
||||
set_location_assignment PIN_62 -to ga[4]
|
||||
set_location_assignment PIN_63 -to n_gm1
|
||||
set_location_assignment PIN_65 -to ga[3]
|
||||
set_location_assignment PIN_66 -to ga[2]
|
||||
set_location_assignment PIN_68 -to ga[0]
|
||||
set_location_assignment PIN_69 -to gma[16]
|
||||
set_location_assignment PIN_70 -to gma[17]
|
||||
set_location_assignment PIN_71 -to gd[0]
|
||||
set_location_assignment PIN_72 -to gd[7]
|
||||
set_location_assignment PIN_74 -to gd[6]
|
||||
set_location_assignment PIN_75 -to gd[1]
|
||||
set_location_assignment PIN_78 -to gd[5]
|
||||
set_location_assignment PIN_79 -to gd[2]
|
||||
set_location_assignment PIN_80 -to gd[3]
|
||||
set_location_assignment PIN_81 -to gd[4]
|
||||
set_location_assignment PIN_82 -to n_grd
|
||||
set_location_assignment PIN_83 -to n_gram
|
||||
set_location_assignment PIN_84 -to n_gwr
|
||||
set_location_assignment PIN_86 -to gma[18]
|
||||
set_location_assignment PIN_87 -to gma[15]
|
||||
set_location_assignment PIN_88 -to n_grom
|
||||
set_location_assignment PIN_90 -to cfg[0]
|
||||
set_location_assignment PIN_91 -to cfg[1]
|
||||
set_location_assignment PIN_92 -to cfg[2]
|
||||
set_location_assignment PIN_98 -to a[8]
|
||||
set_location_assignment PIN_99 -to n_wait
|
||||
set_location_assignment PIN_100 -to a[12]
|
||||
set_location_assignment PIN_101 -to a[9]
|
||||
set_location_assignment PIN_102 -to a[11]
|
||||
set_location_assignment PIN_103 -to a[10]
|
||||
set_location_assignment PIN_107 -to n_iorq
|
||||
set_location_assignment PIN_108 -to d[7]
|
||||
set_location_assignment PIN_109 -to n_wr
|
||||
set_location_assignment PIN_110 -to d[6]
|
||||
set_location_assignment PIN_111 -to n_rd
|
||||
set_location_assignment PIN_112 -to d[5]
|
||||
set_location_assignment PIN_113 -to n_iorqge
|
||||
set_location_assignment PIN_116 -to a[13]
|
||||
set_location_assignment PIN_117 -to d[4]
|
||||
set_location_assignment PIN_118 -to d[3]
|
||||
set_location_assignment PIN_119 -to a[15]
|
||||
set_location_assignment PIN_120 -to a[14]
|
||||
set_location_assignment PIN_121 -to n_m1
|
||||
set_location_assignment PIN_132 -to a[7]
|
||||
set_location_assignment PIN_133 -to a[6]
|
||||
set_location_assignment PIN_134 -to a[4]
|
||||
set_location_assignment PIN_136 -to a[3]
|
||||
set_location_assignment PIN_137 -to a[2]
|
||||
set_location_assignment PIN_138 -to a[1]
|
||||
set_location_assignment PIN_139 -to a[0]
|
||||
set_location_assignment PIN_140 -to a[5]
|
||||
set_location_assignment PIN_141 -to d[0]
|
||||
set_location_assignment PIN_142 -to d[1]
|
||||
set_location_assignment PIN_128 -to clk32
|
||||
set_location_assignment PIN_127 -to rst_n
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name SYNTHESIS_SEED 1
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
|
||||
set_location_assignment PIN_125 -to clkx
|
||||
Reference in New Issue
Block a user