uzix/zx-minidin9lift
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final version

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UzixLS
2020-05-17 13:32:01 +03:00
parent 9c61c8a958
commit 65276aa604
6 changed files with 291 additions and 0 deletions
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1
README.txt Normal file
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Tiny PCB to lift-up minidin-9 connector on ZX Spectrum clones. It allow to fit connector in standard rubber case without modifications.

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out/gerber.zip Normal file
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pcb/minidinexpander-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# my_Mini-DIN-9
#
DEF my_Mini-DIN-9 J 0 40 Y Y 1 F N
F0 "J" 200 200 50 H V C CNN
F1 "my_Mini-DIN-9" 420 -200 50 H V C CNN
F2 "" -10 -10 50 V I C CNN
F3 "" -10 -10 50 V I C CNN
$FPLIST
MINI?DIN*
$ENDFPLIST
DRAW
A 0 0 200 -1269 -531 0 1 10 f -120 -160 120 -160
A 2 4 200 1021 -1488 0 1 10 f -40 200 -170 -100
A 2 5 198 -320 790 0 1 10 f 170 -100 40 200
C -130 0 20 0 1 0 F
C -80 -100 20 0 1 0 F
C -80 100 20 0 1 0 F
C -43 0 20 0 1 0 F
C 1 100 20 0 1 0 F
C 43 0 20 0 1 0 F
C 80 -100 20 0 1 0 F
C 90 100 20 0 1 0 F
C 130 0 20 0 1 0 F
S 121 -161 -113 169 0 1 -39 N
S 121 -159 -121 168 0 1 -39 f
S 169 -100 -169 -14 0 1 -39 f
P 2 0 1 0 -150 0 -200 0 N
P 2 0 1 0 -100 100 -200 100 N
P 2 0 1 0 -42 -160 -42 -20 N
P 2 0 1 0 0 123 0 200 N
P 2 0 1 0 44 -160 44 -20 N
P 2 0 1 0 110 100 200 100 N
P 2 0 1 0 200 0 150 0 N
P 3 0 1 10 -170 -100 -120 -100 -120 -160 N
P 3 0 1 0 -42 -160 -75 -160 -75 -201 N
P 3 0 1 0 45 -160 75 -160 75 -200 N
P 3 0 1 10 170 -100 120 -100 120 -160 N
P 4 0 1 0 -80 -120 -80 -140 -200 -140 -200 -100 N
P 4 0 1 10 -40 200 -40 170 40 170 40 200 N
P 4 0 1 0 80 -120 80 -140 200 -140 200 -100 N
X ~ 0 0 -300 100 U 50 50 1 1 P
X ~ 1 300 -100 100 L 50 50 1 1 P
X ~ 2 -300 -100 100 R 50 50 1 1 P
X ~ 3 300 0 100 L 50 50 1 1 P
X ~ 4 75 -300 100 U 50 50 1 1 P
X ~ 5 -75 -300 100 U 50 50 1 1 P
X ~ 6 -300 0 100 R 50 50 1 1 P
X ~ 7 300 100 100 L 50 50 1 1 P
X ~ 8 0 300 100 D 50 50 1 1 P
X ~ 9 -300 100 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

173
pcb/minidinexpander.kicad_pcb Normal file
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(kicad_pcb (version 20171130) (host pcbnew "(5.1.4)-1")
(general
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(drawings 4)
(tracks 0)
(zones 0)
(modules 1)
(nets 2)
)
(page A4)
(layers
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(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
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(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
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(uvias_allowed no)
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(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
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(usegerberadvancedattributes true)
(creategerberjobfile false)
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(drillshape 0)
(scaleselection 1)
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(add_net "Net-(J1-Pad0)")
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(at 141.518 97.738 180)
(descr "MiniDin 8 (S-Video), Tyco P/N 1734096-1")
(path /5DED40CD)
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(pad 0 thru_hole circle (at -7.112 0.762 180) (size 3.50012 3.50012) (drill 2.19964) (layers *.Cu *.Mask)
(net 1 "Net-(J1-Pad0)"))
(pad 0 thru_hole circle (at 7.239 0.762 180) (size 3.50012 3.50012) (drill 2.19964) (layers *.Cu *.Mask)
(net 1 "Net-(J1-Pad0)"))
(pad 6 thru_hole circle (at -3.8608 -1.6256 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
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(pad 3 thru_hole circle (at 3.8862 -1.6256 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at 0 -4.43738 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at 1.9558 -4.43738 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -3.8608 -4.43738 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at -1.9304 -4.43738 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at 3.8862 -4.43738 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(pad 0 thru_hole roundrect (at 0 1.651 180) (size 3.50012 3.50012) (drill oval 3 1) (layers *.Cu *.Mask) (roundrect_rratio 0.214)
(net 1 "Net-(J1-Pad0)"))
(pad 1 thru_hole circle (at 1.4986 -1.6256 180) (size 1.50114 1.50114) (drill 0.89916) (layers *.Cu *.Mask))
(model walter/conn_av/minidin-8.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
(model E:/ws/hwlib/ki3d/a-dio-fs08.stp
(offset (xyz 0 -6.5 6.5))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(gr_line (start 132.26 104.596) (end 132.26 90.88) (layer Edge.Cuts) (width 0.05))
(gr_line (start 150.662 104.596) (end 132.26 104.596) (layer Edge.Cuts) (width 0.05))
(gr_line (start 150.662 90.88) (end 150.662 104.596) (layer Edge.Cuts) (width 0.05))
(gr_line (start 132.26 90.88) (end 150.662 90.88) (layer Edge.Cuts) (width 0.05))
)

33
pcb/minidinexpander.pro Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

27
pcb/minidinexpander.sch Normal file
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L my:Mini-DIN-9 J1
U 1 1 5DED40CD
P 5925 3700
F 0 "J1" H 5925 4181 50 0000 C CNN
F 1 "Mini-DIN-9" H 5925 4090 50 0000 C CNN
F 2 "my:minidin-9" V 5915 3690 50 0001 C CNN
F 3 "http://service.powerdynamics.com/ec/Catalog17/Section%2011.pdf" V 5915 3690 50 0001 C CNN
1 5925 3700
1 0 0 -1
$EndComp
$EndSCHEMATC