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43 lines
749 B
Verilog
43 lines
749 B
Verilog
`timescale 100ns/1ns
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`define BITS 4
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`define SCALE 0.7
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module testbench_pwldac();
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integer d [0:`BITS-1];
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integer i;
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initial begin
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//$dumpfile("testbench.vcd");
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//$dumpvars();
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for (i = 0; i < `BITS; i = i + 1) begin
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d[i] = $fopen($sformatf("d%0dpwl.txt", i),"w");
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end
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$timeformat(0, 10, "", 0);
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#10000;
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for (i = 0; i < `BITS; i = i + 1) begin
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$fclose(d[i]);
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end
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$finish;
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end
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reg clk;
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always begin
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clk = 0; #300;
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clk = 1; #300;
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end
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reg [`BITS-1:0] cnt = 0;
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reg [`BITS-1:0] cnt_prev = 0;
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always @(posedge clk) begin
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cnt_prev <= cnt;
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cnt <= cnt + 1'b1;
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for (i = 0; i < `BITS; i = i + 1) begin
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$fwrite(d[i], "%t %f\n", $time*10, cnt_prev[i]*`SCALE);
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$fwrite(d[i], "%t00001 %f\n", $time*10, cnt[i]*`SCALE);
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end
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end
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endmodule
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