diff --git a/.gitignore b/.gitignore index 6d8e43b..0151f06 100755 --- a/.gitignore +++ b/.gitignore @@ -8,6 +8,13 @@ pcb/**/*.xml pcb/**/out/ +## LTSpice +spice/work +spice/*.txt +spice/*.raw +spice/*.log +spice/*.vcd + ## Etc. *.bak *.*~ diff --git a/spice/Makefile b/spice/Makefile new file mode 100644 index 0000000..1c675ca --- /dev/null +++ b/spice/Makefile @@ -0,0 +1,24 @@ +export PATH:=/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH} + +all: testbench_pwldac + +testbench_pwldac: V=testbench_pwldac.v + + +# testbench_%: +# iverilog -g2005-sv ${VFLAGS} -o $@.vvp $@.v ${V} +# vvp $@.vvp +# @rm $@.vvp + +testbench_%: + test ! -d work || rm -rf work + vlib work + test ! -n "$(filter %.v,${V})" || vlog -sv $(filter %.v,${V}) + test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom $(filter %.vhd %.vhdl,${V}) + vsim -do 'run -all' $@ + @rm transcript + +%.bin: %.asm + sjasmplus $< +%.mem: %.bin + srec_cat $< -binary -o $@ -vmem 8 diff --git a/spice/rgb2ypbpr.A.asc b/spice/rgb2ypbpr.A.asc new file mode 100644 index 0000000..cd099f1 --- /dev/null +++ b/spice/rgb2ypbpr.A.asc @@ -0,0 +1,246 @@ +Version 4 +SHEET 1 1248 680 +WIRE 1040 -512 656 -512 +WIRE 528 -464 480 -464 +WIRE 592 -464 528 -464 +WIRE 128 -416 96 -416 +WIRE 256 -416 192 -416 +WIRE 352 -416 352 -432 +WIRE 352 -416 336 -416 +WIRE 416 -416 352 -416 +WIRE 784 -240 704 -240 +WIRE 704 -208 704 -240 +WIRE 1040 -208 1040 -512 +WIRE 352 -160 256 -160 +WIRE 416 -160 352 -160 +WIRE 528 -160 416 -160 +WIRE 624 -160 624 -240 +WIRE 624 -160 608 -160 +WIRE 640 -160 624 -160 +WIRE 784 -160 784 -240 +WIRE 816 -160 784 -160 +WIRE 944 -112 880 -112 +WIRE 1040 -112 1040 -128 +WIRE 1040 -112 1024 -112 +WIRE 1088 -112 1040 -112 +WIRE 1200 -112 1152 -112 +WIRE 1040 -96 1040 -112 +WIRE 1200 -96 1200 -112 +WIRE 416 -80 416 -160 +WIRE 352 -32 352 -80 +WIRE 128 64 96 64 +WIRE 240 64 128 64 +WIRE 352 64 352 -32 +WIRE 352 64 320 64 +WIRE 608 64 448 64 +WIRE 128 112 128 64 +WIRE 368 112 128 112 +WIRE 448 112 448 64 +WIRE 528 112 528 -160 +WIRE 784 112 672 112 +WIRE 240 160 96 160 +WIRE 352 160 352 64 +WIRE 352 160 320 160 +WIRE 368 208 128 208 +WIRE 528 208 528 112 +WIRE 128 256 128 208 +WIRE 128 256 96 256 +WIRE 240 256 128 256 +WIRE 352 256 352 160 +WIRE 352 256 320 256 +WIRE 448 256 448 208 +WIRE 608 256 448 256 +WIRE 352 288 352 256 +WIRE 784 304 672 304 +FLAG -192 160 0 +FLAG 16 64 0 +FLAG 16 160 0 +FLAG 16 256 0 +FLAG -192 80 5 +FLAG 352 368 0 +FLAG 416 16 0 +FLAG 256 -240 5 +FLAG 256 -80 0 +FLAG 704 -48 0 +FLAG 784 -320 5 +FLAG 880 -208 5 +FLAG 1040 -16 0 +FLAG 1200 -16 0 +FLAG 16 -416 0 +FLAG 352 -512 5 +FLAG 480 -368 0 +FLAG 528 -544 5 +FLAG 656 -416 0 +FLAG 672 16 5 +FLAG 672 208 5 +FLAG 784 192 0 +FLAG 784 384 0 +SYMBOL voltage -192 64 R0 +WINDOW 0 -32 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V7 +SYMATTR Value 5 +SYMBOL voltage 112 256 R90 +WINDOW 0 -32 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value PWL file=d2pwl.txt +SYMBOL voltage 112 160 R90 +WINDOW 0 -32 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value PWL file=d1pwl.txt +SYMBOL voltage 112 64 R90 +WINDOW 0 -32 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V6 +SYMATTR Value PWL file=d0pwl.txt +SYMBOL res 336 48 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R1 +SYMATTR Value 1k +SYMBOL res 336 144 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R2 +SYMATTR Value 500 +SYMBOL res 336 240 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R3 +SYMATTR Value 2k +SYMBOL res 368 384 R180 +WINDOW 0 36 76 Left 2 +WINDOW 3 36 40 Left 2 +SYMATTR InstName R4 +SYMATTR Value 1k +SYMBOL npn 352 -80 R0 +SYMATTR InstName Q1 +SYMATTR Value BC547B +SYMBOL res 336 -176 R0 +SYMATTR InstName R5 +SYMATTR Value 500 +SYMBOL res 240 -176 R0 +SYMATTR InstName R6 +SYMATTR Value 1k +SYMBOL res 240 -256 R0 +SYMATTR InstName R7 +SYMATTR Value 500 +SYMBOL res 624 -176 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R8 +SYMATTR Value 500 +SYMBOL res 544 96 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R9 +SYMATTR Value 2k +SYMBOL res 544 192 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R10 +SYMATTR Value 2k +SYMBOL npn 640 -208 R0 +SYMATTR InstName Q2 +SYMATTR Value BC547B +SYMBOL res 720 -256 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R11 +SYMATTR Value 1k +SYMBOL diode 688 -112 R0 +SYMATTR InstName D1 +SYMATTR Value 1N4148 +SYMBOL res 768 -336 R0 +SYMATTR InstName R12 +SYMATTR Value 500 +SYMBOL npn 816 -208 R0 +SYMATTR InstName Q3 +SYMATTR Value BC547B +SYMBOL res 1040 -128 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R13 +SYMATTR Value 10 +SYMBOL res 1024 -224 R0 +SYMATTR InstName R14 +SYMATTR Value 15 +SYMBOL res 1024 -112 R0 +SYMATTR InstName R15 +SYMATTR Value 75 +SYMBOL res 1184 -112 R0 +SYMATTR InstName R16 +SYMATTR Value 75 +SYMBOL voltage 112 -416 R90 +WINDOW 0 -32 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value PULSE(1 0 0 1n 1n 4.7m 1) +SYMBOL res 352 -432 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R17 +SYMATTR Value 1k +SYMBOL res 336 -528 R0 +SYMATTR InstName R18 +SYMATTR Value 10k +SYMBOL npn 416 -464 R0 +SYMATTR InstName Q4 +SYMATTR Value BC547B +SYMBOL res 512 -560 R0 +SYMATTR InstName R19 +SYMATTR Value 500 +SYMBOL npn 592 -512 R0 +SYMATTR InstName Q5 +SYMATTR Value BC547B +SYMBOL res 464 96 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R20 +SYMATTR Value 8k +SYMBOL res 464 192 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R21 +SYMATTR Value 8k +SYMBOL npn 608 16 R0 +SYMATTR InstName Q6 +SYMATTR Value BC547B +SYMBOL npn 608 208 R0 +SYMATTR InstName Q7 +SYMATTR Value BC547B +SYMBOL res 768 96 R0 +SYMATTR InstName R22 +SYMATTR Value 75 +SYMBOL res 768 288 R0 +SYMATTR InstName R23 +SYMATTR Value 75 +SYMBOL polcap 128 -400 R270 +WINDOW 0 32 32 VTop 2 +WINDOW 3 0 32 VBottom 2 +SYMATTR InstName C1 +SYMATTR Value 22µ +SYMATTR Description Capacitor +SYMATTR Type cap +SYMATTR SpiceLine V=16 Irms=0 Rser=11 Lser=0 +SYMBOL polcap 1088 -96 R270 +WINDOW 0 32 32 VTop 2 +WINDOW 3 0 32 VBottom 2 +SYMATTR InstName C2 +SYMATTR Value 470µ +SYMATTR Description Capacitor +SYMATTR Type cap +SYMATTR SpiceLine V=16 Irms=395m Rser=0.2 Lser=0 mfg="Nichicon" pn="UPR1C471MPH" type="Al electrolytic" +TEXT -216 -8 Left 2 !.tran 20m diff --git a/spice/testbench_pwldac.v b/spice/testbench_pwldac.v new file mode 100644 index 0000000..7b44546 --- /dev/null +++ b/spice/testbench_pwldac.v @@ -0,0 +1,42 @@ +`timescale 100ns/1ns + +`define BITS 4 +`define SCALE 0.7 + +module testbench_pwldac(); +integer d [0:`BITS-1]; +integer i; + +initial begin + //$dumpfile("testbench.vcd"); + //$dumpvars(); + for (i = 0; i < `BITS; i = i + 1) begin + d[i] = $fopen($sformatf("d%0dpwl.txt", i),"w"); + end + $timeformat(0, 10, "", 0); + #10000; + for (i = 0; i < `BITS; i = i + 1) begin + $fclose(d[i]); + end + $finish; +end + +reg clk; +always begin + clk = 0; #300; + clk = 1; #300; +end + +reg [`BITS-1:0] cnt = 0; +reg [`BITS-1:0] cnt_prev = 0; +always @(posedge clk) begin + cnt_prev <= cnt; + cnt <= cnt + 1'b1; + for (i = 0; i < `BITS; i = i + 1) begin + $fwrite(d[i], "%t %f\n", $time*10, cnt_prev[i]*`SCALE); + $fwrite(d[i], "%t00001 %f\n", $time*10, cnt[i]*`SCALE); + end +end + + +endmodule