diff --git a/fpga/clocks.sdc b/fpga/clocks.sdc new file mode 100644 index 0000000..8f15b0d --- /dev/null +++ b/fpga/clocks.sdc @@ -0,0 +1,4 @@ +create_clock -period 80MHz -name {clk_80mhz} [get_ports {clk_a}] + +derive_clock_uncertainty +derive_pll_clocks -use_tan_name diff --git a/fpga/ncomp.qpf b/fpga/ncomp.qpf new file mode 100644 index 0000000..be93860 --- /dev/null +++ b/fpga/ncomp.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 12:25:28 November 14, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "12:25:28 November 14, 2019" + +# Revisions + +PROJECT_REVISION = "ncomp" diff --git a/fpga/ncomp.qsf b/fpga/ncomp.qsf new file mode 100644 index 0000000..e634b30 --- /dev/null +++ b/fpga/ncomp.qsf @@ -0,0 +1,196 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 12:25:28 November 14, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ncomp_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:25:28 NOVEMBER 14, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_66 -to usb_dn +set_location_assignment PIN_67 -to usb_dp +set_location_assignment PIN_217 -to vga_vsync +set_location_assignment PIN_224 -to vga_g[7] +set_location_assignment PIN_12 -to vga_r[0] +set_location_assignment PIN_13 -to vga_r[1] +set_location_assignment PIN_14 -to vga_r[2] +set_location_assignment PIN_223 -to vga_r[3] +set_location_assignment PIN_222 -to vga_r[4] +set_location_assignment PIN_219 -to vga_r[5] +set_location_assignment PIN_218 -to vga_r[7] +set_location_assignment PIN_234 -to vga_r[6] +set_location_assignment PIN_17 -to vga_g[0] +set_location_assignment PIN_18 -to vga_g[1] +set_location_assignment PIN_233 -to vga_g[2] +set_location_assignment PIN_228 -to vga_g[3] +set_location_assignment PIN_227 -to vga_g[4] +set_location_assignment PIN_226 -to vga_g[5] +set_location_assignment PIN_225 -to vga_g[6] +set_location_assignment PIN_216 -to vga_hsync +set_location_assignment PIN_19 -to vga_b[0] +set_location_assignment PIN_20 -to vga_b[1] +set_location_assignment PIN_21 -to vga_b[2] +set_location_assignment PIN_166 -to vga_b[3] +set_location_assignment PIN_167 -to vga_b[4] +set_location_assignment PIN_168 -to vga_b[5] +set_location_assignment PIN_170 -to vga_b[6] +set_location_assignment PIN_169 -to vga_b[7] +set_global_assignment -name FMAX_REQUIREMENT "80 MHz" -section_id clk_80mhz +set_location_assignment PIN_78 -to led_center +set_location_assignment PIN_77 -to led_right +set_location_assignment PIN_214 -to keyboard_clk +set_location_assignment PIN_215 -to keyboard_dat +set_location_assignment PIN_208 -to mouse_dat +set_location_assignment PIN_213 -to mouse_clk +set_location_assignment PIN_64 -to pcm_bck +set_location_assignment PIN_57 -to pcm_dout +set_location_assignment PIN_65 -to pcm_lrck +set_location_assignment PIN_63 -to pcm_scki +set_location_assignment PIN_236 -to snd_l +set_location_assignment PIN_237 -to snd_r +set_location_assignment PIN_200 -to dram_dq[0] +set_location_assignment PIN_197 -to dram_dq[1] +set_location_assignment PIN_196 -to dram_dq[2] +set_location_assignment PIN_195 -to dram_dq[3] +set_location_assignment PIN_194 -to dram_dq[4] +set_location_assignment PIN_193 -to dram_dq[5] +set_location_assignment PIN_188 -to dram_dq[6] +set_location_assignment PIN_187 -to dram_dq[7] +set_location_assignment PIN_108 -to dram_dq[9] +set_location_assignment PIN_107 -to dram_dq[10] +set_location_assignment PIN_106 -to dram_dq[11] +set_location_assignment PIN_105 -to dram_dq[12] +set_location_assignment PIN_104 -to dram_dq[13] +set_location_assignment PIN_101 -to dram_dq[14] +set_location_assignment PIN_100 -to dram_dq[15] +set_location_assignment PIN_164 -to dram_dq[17] +set_location_assignment PIN_162 -to dram_dq[19] +set_location_assignment PIN_161 -to dram_dq[20] +set_location_assignment PIN_160 -to dram_dq[21] +set_location_assignment PIN_159 -to dram_dq[22] +set_location_assignment PIN_158 -to dram_dq[23] +set_location_assignment PIN_133 -to dram_dq[24] +set_location_assignment PIN_132 -to dram_dq[25] +set_location_assignment PIN_128 -to dram_dq[27] +set_location_assignment PIN_127 -to dram_dq[28] +set_location_assignment PIN_126 -to dram_dq[29] +set_location_assignment PIN_125 -to dram_dq[30] +set_location_assignment PIN_124 -to dram_dq[31] +set_location_assignment PIN_186 -to dram_dqm[0] +set_location_assignment PIN_114 -to dram_dqm[1] +set_location_assignment PIN_173 -to dram_dqm[2] +set_location_assignment PIN_123 -to dram_dqm[3] +set_location_assignment PIN_182 -to dram_ras +set_location_assignment PIN_185 -to dram_we +set_location_assignment PIN_183 -to dram_cs +set_location_assignment PIN_115 -to dram_clk +set_location_assignment PIN_181 -to dram_cas +set_location_assignment PIN_179 -to dram_ba[0] +set_location_assignment PIN_178 -to dram_ba[1] +set_location_assignment PIN_176 -to dram_a[0] +set_location_assignment PIN_184 -to dram_a[11] +set_location_assignment PIN_177 -to dram_a[10] +set_location_assignment PIN_116 -to dram_a[9] +set_location_assignment PIN_119 -to dram_a[8] +set_location_assignment PIN_120 -to dram_a[7] +set_location_assignment PIN_118 -to dram_a[6] +set_location_assignment PIN_117 -to dram_a[5] +set_location_assignment PIN_121 -to dram_a[4] +set_location_assignment PIN_122 -to dram_a[3] +set_location_assignment PIN_174 -to dram_a[2] +set_location_assignment PIN_175 -to dram_a[1] +set_location_assignment PIN_113 -to dram_dq[8] +set_location_assignment PIN_131 -to dram_dq[26] +set_location_assignment PIN_163 -to dram_dq[18] +set_location_assignment PIN_165 -to dram_dq[16] +set_location_assignment PIN_203 -to eth_col +set_location_assignment PIN_202 -to eth_txen +set_location_assignment PIN_201 -to eth_txd[3] +set_location_assignment PIN_134 -to eth_txd[2] +set_location_assignment PIN_135 -to eth_txd[1] +set_location_assignment PIN_136 -to eth_txd[0] +set_location_assignment PIN_137 -to eth_txc +set_location_assignment PIN_138 -to eth_rxc +set_location_assignment PIN_139 -to eth_rxd[3] +set_location_assignment PIN_140 -to eth_rxd[2] +set_location_assignment PIN_141 -to eth_rxd[1] +set_location_assignment PIN_143 -to eth_rxd[0] +set_location_assignment PIN_144 -to eth_rxdv +set_location_assignment PIN_156 -to eth_crs +set_location_assignment PIN_180 -to eth_rxer +set_location_assignment PIN_206 -to eth_mdc +set_location_assignment PIN_99 -to eth_x1 +set_location_assignment PIN_207 -to eth_mdio +set_location_assignment PIN_73 -to max[0] +set_location_assignment PIN_74 -to max[1] +set_location_assignment PIN_79 -to max[2] +set_location_assignment PIN_82 -to max[3] +set_location_assignment PIN_84 -to max[4] +set_location_assignment PIN_83 -to max[5] +set_location_assignment PIN_86 -to max[6] +set_location_assignment PIN_87 -to max[7] +set_location_assignment PIN_88 -to max[8] +set_location_assignment PIN_94 -to max[9] +set_location_assignment PIN_95 -to max[10] +set_location_assignment PIN_93 -to max[11] +set_location_assignment PIN_85 -to max[12] +set_location_assignment PIN_28 -to clk_a +set_location_assignment PIN_153 -to clk_b +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name VHDL_FILE sdram.vhd +set_global_assignment -name VERILOG_FILE vgaout.v +set_global_assignment -name QIP_FILE pll1.qip +set_global_assignment -name VERILOG_FILE top.v +set_global_assignment -name SDC_FILE clocks.sdc +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/pll1.qip b/fpga/pll1.qip new file mode 100644 index 0000000..fadcab7 --- /dev/null +++ b/fpga/pll1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll1.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll1_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll1.ppf"] diff --git a/fpga/pll1.v b/fpga/pll1.v new file mode 100644 index 0000000..f054215 --- /dev/null +++ b/fpga/pll1.v @@ -0,0 +1,307 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll1.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll1 ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [5:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.clk0_divide_by = 8, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 5, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 12500, + altpll_component.intended_device_family = "Cyclone", + altpll_component.invalid_lock_multiplier = 5, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.valid_lock_multiplier = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "80.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "560.000" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "12500" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/fpga/pll1_bb.v b/fpga/pll1_bb.v new file mode 100644 index 0000000..da34d43 --- /dev/null +++ b/fpga/pll1_bb.v @@ -0,0 +1,202 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll1.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2009 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module pll1 ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "80.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "560.000" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "12500" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/fpga/sdram.vhd b/fpga/sdram.vhd new file mode 100644 index 0000000..0cc0386 --- /dev/null +++ b/fpga/sdram.vhd @@ -0,0 +1,271 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity sdram is + generic( + freq : integer := 80 + ); + + port( + clk : in std_logic; + reset : in std_logic; + refresh : in std_logic; + + memAddress : in std_logic_vector(21 downto 0); + memDataIn : in std_logic_vector(31 downto 0); + memDataOut : out std_logic_vector(31 downto 0); + memDataMask : in std_logic_vector(3 downto 0); + memWr : in std_logic; + memReq : in std_logic; + memAck : out std_logic := '0'; + + memAddress2 : in std_logic_vector(21 downto 0); + memDataIn2 : in std_logic_vector(31 downto 0); + memDataOut2 : out std_logic_vector(31 downto 0); + memDataMask2 : in std_logic_vector(3 downto 0); + memWr2 : in std_logic; + memReq2 : in std_logic; + memAck2 : out std_logic := '0'; + + -- SD-RAM ports + pMemClk : out std_logic; -- SD-RAM Clock + pMemCke : out std_logic; -- SD-RAM Clock enable + pMemCs_n : out std_logic; -- SD-RAM Chip select + pMemRas_n : out std_logic; -- SD-RAM Row/RAS + pMemCas_n : out std_logic; -- SD-RAM /CAS + pMemWe_n : out std_logic; -- SD-RAM /WE + pMemDqm : out std_logic_vector(3 downto 0); -- SD-RAM DQM + pMemBa1 : out std_logic; -- SD-RAM Bank select address 1 + pMemBa0 : out std_logic; -- SD-RAM Bank select address 0 + pMemAdr : out std_logic_vector(11 downto 0); -- SD-RAM Address + pMemDat : inout std_logic_vector(31 downto 0) -- SD-RAM Data + ); + +end sdram; + +architecture rtl of sdram is + +-- -- SD-RAM control signals + signal SdrCmd : std_logic_vector(3 downto 0); + signal SdrBa0 : std_logic; + signal SdrBa1 : std_logic; + signal SdrDqm : std_logic_vector(3 downto 0); + signal SdrAdr : std_logic_vector(11 downto 0); + signal SdrDat : std_logic_vector(31 downto 0); + + signal iMemAck : std_logic; + signal iMemAck2 : std_logic; + + constant SdrCmd_de : std_logic_vector(3 downto 0) := "1111"; -- deselect + constant SdrCmd_pr : std_logic_vector(3 downto 0) := "0010"; -- precharge all + constant SdrCmd_re : std_logic_vector(3 downto 0) := "0001"; -- refresh + constant SdrCmd_ms : std_logic_vector(3 downto 0) := "0000"; -- mode regiser set + constant SdrCmd_xx : std_logic_vector(3 downto 0) := "0111"; -- no operation + constant SdrCmd_ac : std_logic_vector(3 downto 0) := "0011"; -- activate + constant SdrCmd_rd : std_logic_vector(3 downto 0) := "0101"; -- read + constant SdrCmd_wr : std_logic_vector(3 downto 0) := "0100"; -- write + +begin + + memAck <= iMemAck; + memAck2 <= iMemAck2; + + process( clk ) + + type typSdrRoutine is ( SdrRoutine_Null, SdrRoutine_Init, SdrRoutine_Idle, SdrRoutine_RefreshAll, SdrRoutine_ReadOne, SdrRoutine_WriteOne ); + variable SdrRoutine : typSdrRoutine := SdrRoutine_Null; + variable SdrRoutineSeq : unsigned(7 downto 0) := X"00"; + + variable refreshDelayCounter : unsigned(23 downto 0) := x"000000"; + variable SdrRefreshCounter : unsigned(15 downto 0) := X"0000"; + + variable SdrPort : std_logic := '0'; + variable SdrAddress : std_logic_vector(21 downto 0); + + begin + + if clk'event and clk = '1' then + + iMemAck <= '0'; + iMemAck2 <= '0'; + + case SdrRoutine is + + when SdrRoutine_Null => + SdrCmd <= SdrCmd_xx; + SdrDat <= (others => 'Z'); + + if refreshDelayCounter = 0 then + SdrRoutine := SdrRoutine_Init; + end if; + + when SdrRoutine_Init => + if( SdrRoutineSeq = X"0" ) then + SdrCmd <= SdrCmd_pr; + SdrAdr <= "111111111111"; + SdrBa1 <= '0'; + SdrBa0 <= '0'; + SdrDqm <= "1111"; + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"4" or SdrRoutineSeq = X"0C" ) then + SdrCmd <= SdrCmd_re; + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"14" ) then + SdrCmd <= SdrCmd_ms; + SdrAdr <= "000" & "0" & "0" & "010" & "0" & "000"; + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"17" ) then + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := X"00"; + SdrRoutine := SdrRoutine_Idle; + else + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := SdrRoutineSeq + 1; + end if; + + when SdrRoutine_Idle => + SdrCmd <= SdrCmd_xx; + SdrDat <= (others => 'Z'); + + if memReq = '1' and iMemAck = '0' then + SdrPort := '0'; + SdrAddress := memAddress; + + if( memWr = '1' ) then + SdrRoutine := SdrRoutine_WriteOne; + else + SdrRoutine := SdrRoutine_ReadOne; + end if; + + elsif memReq2 = '1' and iMemAck2 = '0' then + SdrPort := '1'; + SdrAddress := memAddress2; + + if( memWr2 = '1' ) then + SdrRoutine := SdrRoutine_WriteOne; + else + SdrRoutine := SdrRoutine_ReadOne; + end if; + + + elsif SdrRefreshCounter < 4096 and refresh = '1' then + SdrRoutine := SdrRoutine_RefreshAll; + SdrRefreshCounter := SdrRefreshCounter + 1; + end if; + + when SdrRoutine_RefreshAll => + if( SdrRoutineSeq = X"0" ) then + SdrCmd <= SdrCmd_re; + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"6" ) then + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := X"00"; + SdrRoutine := SdrRoutine_Idle; + else + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := SdrRoutineSeq + 1; + end if; + + when SdrRoutine_ReadOne => + if( SdrRoutineSeq = X"0" ) then + SdrCmd <= SdrCmd_ac; + SdrBa0 <= SdrAddress(20); + SdrBa1 <= SdrAddress(21); + SdrAdr <= SdrAddress(19 downto 8); + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"2" ) then + SdrCmd <= SdrCmd_rd; + SdrDqm <= "0000"; + SdrAdr(11 downto 8) <= "0100"; + SdrAdr(7 downto 0) <= SdrAddress(7 downto 0); + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"5" ) then + if( SdrPort = '0' ) then + memDataOut <= pMemDat; + iMemAck <= '1'; + else + memDataOut2 <= pMemDat; + iMemAck2 <= '1'; + end if; + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"6" ) then + SdrRoutineSeq := X"00"; + SdrRoutine := SdrRoutine_Idle; + else + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := SdrRoutineSeq + 1; + end if; + + when SdrRoutine_WriteOne => + if( SdrRoutineSeq = X"0" ) then + SdrCmd <= SdrCmd_ac; + SdrBa0 <= SdrAddress(20); + SdrBa1 <= SdrAddress(21); + SdrAdr <= SdrAddress(19 downto 8); + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"2" ) then + SdrCmd <= SdrCmd_wr; + SdrAdr(11 downto 8) <= "0100"; + SdrAdr(7 downto 0) <= SdrAddress(7 downto 0); + if( SdrPort = '0' ) then + SdrDat <= memDataIn; + SdrDqm(0) <= not memDataMask(0); + SdrDqm(1) <= not memDataMask(1); + SdrDqm(2) <= not memDataMask(2); + SdrDqm(3) <= not memDataMask(3); + else + SdrDat <= memDataIn2; + SdrDqm(0) <= not memDataMask2(0); + SdrDqm(1) <= not memDataMask2(1); + SdrDqm(2) <= not memDataMask2(2); + SdrDqm(3) <= not memDataMask2(3); + end if; + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"3" ) then + if( SdrPort = '0' ) then + iMemAck <= '1'; + else + iMemAck2 <= '1'; + end if; + SdrCmd <= SdrCmd_xx; + SdrDat <= (others => 'Z'); + SdrRoutineSeq := SdrRoutineSeq + 1; + elsif( SdrRoutineSeq = X"5" ) then + SdrRoutineSeq := X"00"; + SdrRoutine := SdrRoutine_Idle; + else + SdrCmd <= SdrCmd_xx; + SdrRoutineSeq := SdrRoutineSeq + 1; + end if; + + end case; + + refreshDelayCounter := refreshDelayCounter + 1; + + if( refreshDelayCounter >= ( freq * 1000 * 64 ) ) then + refreshDelayCounter := x"000000"; + SdrRefreshCounter := x"0000"; + end if; + + end if; + + end process; + + pMemClk <= not clk; + pMemCke <= '1'; + + pMemCs_n <= SdrCmd(3); + pMemRas_n <= SdrCmd(2); + pMemCas_n <= SdrCmd(1); + pMemWe_n <= SdrCmd(0); + + pMemDqm <= SdrDqm; + pMemBa1 <= SdrBa1; + pMemBa0 <= SdrBa0; + + pMemAdr <= SdrAdr; + pMemDat <= SdrDat; + +end rtl; diff --git a/fpga/top.v b/fpga/top.v new file mode 100644 index 0000000..e1e6ae8 --- /dev/null +++ b/fpga/top.v @@ -0,0 +1,156 @@ +module top( + input clk_a, + input clk_b, + + output led_center, + output led_right, + + output [7:0] vga_r, + output [7:0] vga_g, + output [7:0] vga_b, + output vga_hsync, + output vga_vsync, + + output keyboard_clk, + inout keyboard_dat, + output mouse_clk, + inout mouse_dat, + + output snd_l, + output snd_r, + input pcm_dout, + output pcm_scki, + inout pcm_lrck, + inout pcm_bck, + + input eth_txc, + output eth_txen, + output [3:0] eth_txd, + input eth_rxc, + input eth_col, + input eth_crs, + input eth_rxdv, + input [3:0] eth_rxd, + input eth_rxer, + output eth_mdc, + inout eth_mdio, + output eth_x1, + + inout usb_dp, + inout usb_dn, + + output dram_we, + output dram_cas, + output dram_ras, + output dram_cs, + output dram_clk, + output [3:0] dram_dqm, + inout [31:0] dram_dq, + output [1:0] dram_ba, + output [11:0] dram_a, + + inout [12:0] max +); + + +wire pll_locked; +wire rst_n = pll_locked; +wire clk_80mhz = clk_a; +wire clk_50mhz; +pll1 pll1(.inclk0(clk_80mhz), .c0(clk_50mhz), .locked(pll_locked)); + +reg [24:0] cnt; +wire clk_1hz = cnt[24]; +wire clk_3hz = cnt[23]; +wire clk_760khz = cnt[15]; +always @(posedge clk_50mhz or negedge rst_n) begin + if (!rst_n) + cnt <= 0; + else + cnt <= cnt + 1'b1; +end + +assign led_center = clk_1hz; +assign led_right = clk_3hz; + +reg x; +always @(posedge clk_760khz or negedge rst_n) begin + if(!rst_n) + x <= 0; + else + x <= ~x; +end + +wire [9:0] vram_h, vram_v; +wire [23:0] vram_data = { +vram_h[7], vram_h[6], vram_h[5], vram_h[4], vram_h[3], vram_h[2], vram_h[1], vram_h[0], +vram_v[7], vram_v[6], vram_v[5], vram_v[4], vram_v[3], vram_v[2], vram_v[1], vram_v[0], +vram_v[7], vram_v[6], vram_v[5], vram_v[4], vram_v[3], vram_v[2], vram_v[1], vram_v[0], +}; + +vgaout #(.BITS(8), .VRAM_DELAY(5)) vgaout1( + .clk(clk_50mhz), + .rst_n(rst_n), + .hsync(vga_hsync), + .vsync(vga_vsync), + .r(vga_r), + .g(vga_g), + .b(vga_b), + .vram_h(vram_h), + .vram_v(vram_v), + .vram_data(vram_data) +); + + +reg sdram_req; +wire sdram_ack; +wire [21:0] sdram_addr; +wire [31:0] sdram_data_in; +wire [31:0] sdram_data_out; +wire sdram_wren = 0; +wire sdram_rfsh = 0; +sdram sdram1( + .clk(clk_80mhz), + .reset(~rst_n), + .refresh(sdram_rfsh), + + .memAddress(sdram_addr), + .memDataIn(sdram_data_in), + .memDataOut(sdram_data_out), + .memDataMask(4'b1111), + .memWr(sdram_wren), + .memReq(sdram_req), + .memAck(sdram_ack), + + .pMemClk(dram_clk), + .pMemCs_n(dram_cs), + .pMemRas_n(dram_ras), + .pMemCas_n(dram_cas), + .pMemWe_n(dram_we), + .pMemBa1(dram_ba[1]), + .pMemBa0(dram_ba[0]), + .pMemAdr(dram_a), + .pMemDat(dram_dq), + .pMemDqm(dram_dqm) +); + + +reg [8:0] snd_l_acc, snd_r_acc; +reg [7:0] snd_l_data, snd_r_data; +assign snd_l = snd_l_acc[8]; +assign snd_r = snd_r_acc[8]; +always @(posedge clk_50mhz or negedge rst_n) begin + if (!rst_n) begin + snd_l_data <= 0; + snd_r_data <= 0; + snd_l_acc <= 0; + snd_r_acc <= 0; + end + else begin + snd_l_acc <= snd_l_acc[7:0] + snd_l_data; + snd_r_acc <= snd_r_acc[7:0] + snd_r_data; + end +end + + +endmodule diff --git a/fpga/vgaout.v b/fpga/vgaout.v new file mode 100644 index 0000000..febb2bc --- /dev/null +++ b/fpga/vgaout.v @@ -0,0 +1,93 @@ +module vgaout#( + parameter VRAM_DELAY = 2, + parameter BITS = 1, + parameter PIXELS = 800, + parameter H_FRONT_PORCH = 56, + parameter HSYNC_LEN = 120, + parameter H_BACK_PORCH = 64, + parameter LINES = 600, + parameter V_FRONT_PORCH = 37, + parameter VSYNC_LEN = 6, + parameter V_BACK_PORCH = 23, + parameter HSYNC_NEG = 1'b0, + parameter VSYNC_NEG = 1'b0 + ) ( + input clk, + input rst_n, + + output wire [$clog2(PIXELS)-1:0] vram_h, + output wire [$clog2(LINES)-1:0] vram_v, + output wire vram_read, + input wire [3*BITS-1:0] vram_data, + + output reg vblank, + output wire rgb_en, + + output reg hsync, + output reg vsync, + output reg [BITS-1:0] r, + output reg [BITS-1:0] g, + output reg [BITS-1:0] b + ); + + +reg [$clog2(PIXELS+H_FRONT_PORCH+HSYNC_LEN+H_BACK_PORCH)-1:0] hcnt; +reg [$clog2(LINES+V_FRONT_PORCH+VSYNC_LEN+V_BACK_PORCH)-1:0] vcnt; + +wire [BITS-1:0] vram_r, vram_g, vram_b; +assign {vram_r, vram_g, vram_b} = vram_data; + +assign vram_h = hcnt - HSYNC_LEN - H_FRONT_PORCH + VRAM_DELAY; +assign vram_v = vcnt; +assign vram_read = (vcnt < LINES) && (hcnt >= HSYNC_LEN + H_FRONT_PORCH - VRAM_DELAY) + && (hcnt < HSYNC_LEN + H_FRONT_PORCH + PIXELS); + +assign rgb_en = (vcnt < LINES) && (hcnt >= HSYNC_LEN + H_FRONT_PORCH) + && (hcnt < HSYNC_LEN + H_FRONT_PORCH + PIXELS); + + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + hcnt <= 1'b0; + vcnt <= 1'b0; + vblank <= 1'b0; + hsync <= 1'b0; + vsync <= 1'b0; + r <= 1'b0; + g <= 1'b0; + b <= 1'b0; + end else begin + if (hcnt == PIXELS + H_FRONT_PORCH + HSYNC_LEN + H_BACK_PORCH - 1) begin + hcnt <= 1'b0; + if (vcnt == LINES + V_FRONT_PORCH + VSYNC_LEN + V_BACK_PORCH - 1) begin + vcnt <= 1'b0; + end else begin + vcnt <= vcnt + 1'b1; + end + end else begin + hcnt <= hcnt + 1'b1; + vcnt <= vcnt; + end + + vblank <= (vcnt >= LINES); + + hsync <= HSYNC_NEG ^ (hcnt < HSYNC_LEN); + + vsync <= VSYNC_NEG ^ (vcnt >= LINES + V_FRONT_PORCH + && vcnt < LINES + V_FRONT_PORCH + VSYNC_LEN); + + if (rgb_en) begin + r <= vram_r; + g <= vram_g; + b <= vram_b; + end else begin + r <= 1'b0; + g <= 1'b0; + b <= 1'b0; + end + + end +end + + +endmodule