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393 lines
13 KiB
Verilog
393 lines
13 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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`timescale 1ns / 1ps
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module jt12_mmr(
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input rst,
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input clk,
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input cen,
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output clk_en,
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output clk_en_ssg,
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input [7:0] din,
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input write,
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input [1:0] addr,
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output reg busy,
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output ch6op,
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// LFO
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output reg [2:0] lfo_freq,
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output reg lfo_en,
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// Timers
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output reg [9:0] value_A,
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output reg [7:0] value_B,
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output reg load_A,
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output reg load_B,
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output reg enable_irq_A,
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output reg enable_irq_B,
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output reg clr_flag_A,
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output reg clr_flag_B,
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output reg fast_timers,
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input flag_A,
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input overflow_A,
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// PCM
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output reg [8:0] pcm,
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output reg pcm_en,
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output reg pcm_wr, // high for one clock cycle when PCM is written
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// Operator
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output xuse_prevprev1,
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output xuse_internal,
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output yuse_internal,
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output xuse_prev2,
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output yuse_prev1,
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output yuse_prev2,
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// PG
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output [10:0] fnum_I,
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output [ 2:0] block_I,
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output reg pg_stop,
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// REG
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output [ 1:0] rl,
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output [ 2:0] fb_II,
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output [ 2:0] alg_I,
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output [ 2:0] pms_I,
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output [ 1:0] ams_IV,
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output amsen_IV,
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output [ 2:0] dt1_I,
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output [ 3:0] mul_II,
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output [ 6:0] tl_IV,
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output reg eg_stop,
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output [ 4:0] ar_I,
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output [ 4:0] d1r_I,
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output [ 4:0] d2r_I,
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output [ 3:0] rr_I,
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output [ 3:0] sl_I,
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output [ 1:0] ks_II,
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// SSG operation
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output ssg_en_I,
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output [2:0] ssg_eg_I,
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output keyon_I,
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// output [ 1:0] cur_op,
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// Operator
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output zero,
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output s1_enters,
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output s2_enters,
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output s3_enters,
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output s4_enters,
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// PSG interace
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output [3:0] psg_addr,
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output [7:0] psg_data,
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output reg psg_wr_n
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);
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parameter use_ssg=0, num_ch=6, use_pcm=1;
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`ifdef SIMULATION
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initial begin
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cen_cnt = 3'd0;
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end
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`include "jt12_mmr_sim.vh"
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`endif
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reg [1:0] div_setting;
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jt12_div #(.use_ssg(use_ssg),.num_ch(num_ch)) u_div (
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.div_setting ( div_setting ),
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.clk_en ( clk_en ),
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.clk_en_ssg ( clk_en_ssg )
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);
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reg [7:0] selected_register;
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//reg sch; // 0 => CH1~CH3 only available. 1=>CH4~CH6
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/*
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reg irq_zero_en, irq_brdy_en, irq_eos_en,
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irq_tb_en, irq_ta_en;
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*/
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reg [6:0] up_opreg; // hot-one encoding. tells which operator register gets updated next
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reg [2:0] up_chreg; // hot-one encoding. tells which channel register gets updated next
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reg up_keyon;
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wire busy_reg;
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parameter REG_TESTYM = 8'h21,
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REG_LFO = 8'h22,
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REG_CLKA1 = 8'h24,
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REG_CLKA2 = 8'h25,
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REG_CLKB = 8'h26,
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REG_TIMER = 8'h27,
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REG_KON = 8'h28,
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REG_IRQMASK = 8'h29,
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REG_PCM = 8'h2A,
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REG_PCM_EN = 8'h2B,
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REG_DACTEST = 8'h2C,
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REG_CLK_N6 = 8'h2D,
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REG_CLK_N3 = 8'h2E,
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REG_CLK_N2 = 8'h2F;
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reg csm, effect;
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reg [ 2:0] block_ch3op2, block_ch3op3, block_ch3op1;
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reg [10:0] fnum_ch3op2, fnum_ch3op3, fnum_ch3op1;
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reg [ 5:0] latch_fnum;
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reg [2:0] up_ch;
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reg [1:0] up_op;
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reg old_write;
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reg [7:0] din_copy;
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always @(posedge clk)
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old_write <= write;
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generate
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if( use_ssg ) begin
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assign psg_addr = selected_register[3:0];
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assign psg_data = din_copy;
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end else begin
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assign psg_addr = 4'd0;
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assign psg_data = 8'd0;
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end
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endgenerate
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reg part;
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// this runs at clk speed, no clock gating here
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always @(posedge clk) begin : memory_mapped_registers
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if( rst ) begin
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selected_register <= 8'h0;
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div_setting <= 2'b11;
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up_ch <= 3'd0;
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up_op <= 2'd0;
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up_keyon <= 1'd0;
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up_opreg <= 7'd0;
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up_chreg <= 3'd0;
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// IRQ Mask
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/*{ irq_zero_en, irq_brdy_en, irq_eos_en,
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irq_tb_en, irq_ta_en } = 5'h1f; */
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// timers
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{ value_A, value_B } <= 18'd0;
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{ clr_flag_B, clr_flag_A,
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enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;
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fast_timers <= 1'b0;
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// LFO
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lfo_freq <= 3'd0;
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lfo_en <= 1'b0;
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csm <= 1'b0;
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effect <= 1'b0;
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// PCM
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pcm <= 9'h0;
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pcm_en <= 1'b0;
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pcm_wr <= 1'b0;
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// sch <= 1'b0;
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// Original test features
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eg_stop <= 1'b0;
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pg_stop <= 1'b0;
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psg_wr_n <= 1'b1;
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end else begin
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// WRITE IN REGISTERS
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if( write ) begin
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if( !addr[0] ) begin
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selected_register <= din;
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part <= addr[1];
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end else begin
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// Global registers
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din_copy <= din;
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up_keyon <= selected_register == REG_KON;
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up_ch <= {part, selected_register[1:0]};
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up_op <= selected_register[3:2]; // 0=S1,1=S3,2=S2,3=S4
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casez( selected_register)
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//REG_TEST: lfo_rst <= 1'b1; // regardless of din
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8'h0?: psg_wr_n <= 1'b0;
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REG_TESTYM: begin
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eg_stop <= din[5];
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pg_stop <= din[3];
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fast_timers <= din[2];
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end
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REG_CLKA1: value_A[9:2]<= din;
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REG_CLKA2: value_A[1:0]<= din[1:0];
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REG_CLKB: value_B <= din;
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REG_TIMER: begin
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effect <= |din[7:6];
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csm <= din[7:6] == 2'b10;
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{ clr_flag_B, clr_flag_A,
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enable_irq_B, enable_irq_A,
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load_B, load_A } <= din[5:0];
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end
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`ifndef NOLFO
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REG_LFO: { lfo_en, lfo_freq } <= din[3:0];
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`endif
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// clock divider
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REG_CLK_N6: div_setting[1] <= 1'b1;
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REG_CLK_N3: div_setting[0] <= 1'b1;
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REG_CLK_N2: div_setting <= 2'b0;
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// CH3 special registers
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8'hA9: { block_ch3op1, fnum_ch3op1 } <= { latch_fnum, din };
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8'hA8: { block_ch3op3, fnum_ch3op3 } <= { latch_fnum, din };
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8'hAA: { block_ch3op2, fnum_ch3op2 } <= { latch_fnum, din };
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// According to http://www.mjsstuf.x10host.com/pages/vgmPlay/vgmPlay.htm
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// There is a single fnum latch for all channels
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8'hA4, 8'hA5, 8'hA6, 8'hAD, 8'hAC, 8'hAE: latch_fnum <= din[5:0];
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default:; // avoid incomplete-case warning
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endcase
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if( use_pcm==1 ) begin // for YM2612 only
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casez( selected_register)
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REG_DACTEST: pcm[0] <= din[3];
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REG_PCM:
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pcm <= { ~din[7], din[6:0], 1'b1 };
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REG_PCM_EN: pcm_en <= din[7];
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default:;
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endcase
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pcm_wr <= selected_register==REG_PCM;
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end
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if( selected_register[1:0]==2'b11 )
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{ up_chreg, up_opreg } <= { 3'h0, 7'h0 };
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else
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casez( selected_register )
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// channel registers
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8'hA0, 8'hA1, 8'hA2: { up_chreg, up_opreg } <= { 3'h1, 7'd0 }; // up_fnumlo
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// FB + Algorithm
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8'hB0, 8'hB1, 8'hB2: { up_chreg, up_opreg } <= { 3'h2, 7'd0 }; // up_alg
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8'hB4, 8'hB5, 8'hB6: { up_chreg, up_opreg } <= { 3'h4, 7'd0 }; // up_pms
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// operator registers
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8'h3?: { up_chreg, up_opreg } <= { 3'h0, 7'h01 }; // up_dt1
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8'h4?: { up_chreg, up_opreg } <= { 3'h0, 7'h02 }; // up_tl
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8'h5?: { up_chreg, up_opreg } <= { 3'h0, 7'h04 }; // up_ks_ar
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8'h6?: { up_chreg, up_opreg } <= { 3'h0, 7'h08 }; // up_amen_dr
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8'h7?: { up_chreg, up_opreg } <= { 3'h0, 7'h10 }; // up_sr
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8'h8?: { up_chreg, up_opreg } <= { 3'h0, 7'h20 }; // up_sl
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8'h9?: { up_chreg, up_opreg } <= { 3'h0, 7'h40 }; // up_ssgeg
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default: { up_chreg, up_opreg } <= { 3'h0, 7'h0 };
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endcase // selected_register
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end
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end
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else if(clk_en) begin /* clear once-only bits */
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// lfo_rst <= 1'b0;
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{ clr_flag_B, clr_flag_A } <= 2'd0;
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psg_wr_n <= 1'b1;
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pcm_wr <= 1'b0;
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end
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end
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end
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reg [4:0] busy_cnt; // busy lasts for 32 synth clock cycles, like in real chip
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always @(posedge clk)
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if( rst ) begin
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busy <= 1'b0;
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busy_cnt <= 5'd0;
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end
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else begin
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if (!old_write && write && addr[0] ) begin // only set for data writes
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busy <= 1'b1;
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busy_cnt <= 5'd0;
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end
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else if(clk_en) begin
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if( busy_cnt == 5'd31 ) busy <= 1'b0;
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busy_cnt <= busy_cnt+5'd1;
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end
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end
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jt12_reg #(.num_ch(num_ch)) u_reg(
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.rst ( rst ),
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.clk ( clk ), // P1
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.clk_en ( clk_en ),
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.din ( din_copy ),
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.up_keyon ( up_keyon ),
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.up_fnumlo ( up_chreg[0] ),
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.up_alg ( up_chreg[1] ),
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.up_pms ( up_chreg[2] ),
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.up_dt1 ( up_opreg[0] ),
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.up_tl ( up_opreg[1] ),
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.up_ks_ar ( up_opreg[2] ),
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.up_amen_dr ( up_opreg[3] ),
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.up_sr ( up_opreg[4] ),
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.up_sl_rr ( up_opreg[5] ),
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.up_ssgeg ( up_opreg[6] ),
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.op ( up_op ), // operator to update
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.ch ( up_ch ), // channel to update
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.csm ( csm ),
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.flag_A ( flag_A ),
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.overflow_A ( overflow_A),
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.ch6op ( ch6op ),
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// CH3 Effect-mode operation
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.effect ( effect ), // allows independent freq. for CH 3
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.fnum_ch3op2( fnum_ch3op2 ),
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.fnum_ch3op3( fnum_ch3op3 ),
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.fnum_ch3op1( fnum_ch3op1 ),
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.block_ch3op2( block_ch3op2 ),
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.block_ch3op3( block_ch3op3 ),
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.block_ch3op1( block_ch3op1 ),
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.latch_fnum ( latch_fnum ),
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// Operator
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.xuse_prevprev1 ( xuse_prevprev1 ),
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.xuse_internal ( xuse_internal ),
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.yuse_internal ( yuse_internal ),
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.xuse_prev2 ( xuse_prev2 ),
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.yuse_prev1 ( yuse_prev1 ),
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.yuse_prev2 ( yuse_prev2 ),
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// PG
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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.mul_II ( mul_II ),
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.dt1_I ( dt1_I ),
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// EG
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.ar_I (ar_I ), // attack rate
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.d1r_I (d1r_I ), // decay rate
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.d2r_I (d2r_I ), // sustain rate
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.rr_I (rr_I ), // release rate
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.sl_I (sl_I ), // sustain level
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.ks_II (ks_II ), // key scale
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// SSG operation
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.ssg_en_I ( ssg_en_I ),
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.ssg_eg_I ( ssg_eg_I ),
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// envelope number
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.tl_IV (tl_IV ),
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.pms_I (pms_I ),
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.ams_IV (ams_IV ),
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.amsen_IV (amsen_IV ),
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// channel configuration
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.rl ( rl ),
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.fb_II ( fb_II ),
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.alg_I ( alg_I ),
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.keyon_I ( keyon_I ),
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.zero ( zero ),
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.s1_enters ( s1_enters ),
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.s2_enters ( s2_enters ),
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.s3_enters ( s3_enters ),
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.s4_enters ( s4_enters )
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);
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endmodule
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