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43 lines
1.3 KiB
Verilog
43 lines
1.3 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: March, 10th 2017
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*/
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/* Limiting amplifier by 3dB * shift */
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`timescale 1ns / 1ps
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module jt12_limitamp #( parameter width=20, shift=5 ) (
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input signed [width-1:0] left_in,
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input signed [width-1:0] right_in,
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output reg signed [width-1:0] left_out,
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output reg signed [width-1:0] right_out
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);
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always @(*) begin
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left_out = ^left_in[width-1:width-1-shift] ?
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{ left_in[width-1], {(width-1){~left_in[width-1]}}} :
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left_in <<< shift;
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right_out = ^right_in[width-1:width-1-shift] ?
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{ right_in[width-1], {(width-1){~right_in[width-1]}}} :
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right_in <<< shift;
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end
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endmodule
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