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62 lines
1.5 KiB
Verilog
62 lines
1.5 KiB
Verilog
/* This file is part of JT49.
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JT49 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT49 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT49. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-Nov-2018
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Based on sqmusic, by the same author
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*/
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module jt49_noise(
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(* direct_enable *) input cen,
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input clk,
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input rst_n,
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input [4:0] period,
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output reg noise
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);
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reg [5:0]count;
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reg [16:0]poly17;
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wire poly17_zero = poly17==17'b0;
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wire noise_en;
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reg last_en;
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wire noise_up = noise_en && !last_en;
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always @(posedge clk ) if(cen) begin
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noise <= ~poly17[0];
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end
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always @( posedge clk, negedge rst_n )
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if( !rst_n )
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poly17 <= 17'd0;
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else if( cen ) begin
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last_en <= noise_en;
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if( noise_up )
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poly17 <= { poly17[0] ^ poly17[3] ^ poly17_zero, poly17[16:1] };
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end
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jt49_div #(5) u_div(
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.clk ( clk ),
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.cen ( cen ),
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.rst_n ( rst_n ),
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.period ( period ),
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.div ( noise_en )
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);
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endmodule |