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89 lines
2.3 KiB
Verilog
89 lines
2.3 KiB
Verilog
/* This file is part of JT49.
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JT49 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT49 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT49. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-Nov-2018
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Based on sqmusic, by the same author
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*/
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module jt49_eg(
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(* direct_enable *) input cen,
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input clk, // this is the divided down clock from the core
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input step,
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input null_period,
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input rst_n,
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input restart,
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input [3:0] ctrl,
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output reg [4:0]env
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);
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reg inv, stop;
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reg [4:0] gain;
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wire CONT = ctrl[3];
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wire ATT = ctrl[2];
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wire ALT = ctrl[1];
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wire HOLD = ctrl[0];
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wire will_hold = !CONT || HOLD;
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always @(posedge clk)
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if( cen ) env <= inv ? ~gain : gain;
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reg last_step;
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wire step_edge = (step && !last_step) || null_period;
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wire will_invert = (!CONT&&ATT) || (CONT&&ALT);
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reg rst_latch, rst_clr;
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always @(posedge clk) begin
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if( restart ) rst_latch <= 1;
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else if(rst_clr ) rst_latch <= 0;
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end
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always @( posedge clk, negedge rst_n )
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if( !rst_n) begin
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gain <= 5'h1F;
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inv <= 0;
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stop <= 0;
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rst_clr <= 0;
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end
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else if( cen ) begin
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last_step <= step;
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if( rst_latch ) begin
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gain <= 5'h1F;
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inv <= ATT;
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stop <= 1'b0;
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rst_clr <= 1;
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end
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else begin
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rst_clr <= 0;
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if (step_edge && !stop) begin
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if( gain==5'h00 ) begin
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if( will_hold )
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stop <= 1'b1;
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else
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gain <= gain-5'b1;
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if( will_invert ) inv<=~inv;
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end
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else gain <= gain-5'b1;
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end
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end
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end
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endmodule
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