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49 lines
1.5 KiB
Verilog
49 lines
1.5 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 2-11-2018
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Based on information posted by Nemesis on:
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http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
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Based on jt51_phasegen.v, from JT51
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*/
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module jt12_pg_sum (
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input [ 3:0] mul,
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input [19:0] phase_in,
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input pg_rst,
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input signed [5:0] detune_signed,
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input [16:0] phinc_pure,
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output reg [19:0] phase_out,
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output reg [ 9:0] phase_op
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);
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reg [16:0] phinc_premul;
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reg [19:0] phinc_mul;
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always @(*) begin
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phinc_premul = phinc_pure + {{11{detune_signed[5]}},detune_signed};
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phinc_mul = ( mul==4'd0 ) ? {4'b0,phinc_premul[16:1]} : ({3'd0,phinc_premul} * mul);
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phase_out = pg_rst ? 20'd0 : (phase_in + { phinc_mul});
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phase_op = phase_out[19:10];
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end
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endmodule // jt12_pg_sum
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