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81 lines
2.2 KiB
Verilog
81 lines
2.2 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 29-10-2018
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*/
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module jt12_eg_pure(
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input attack,
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input step,
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input [ 5:1] rate,
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input [ 9:0] eg_in,
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input ssg_en,
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input sum_up,
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output reg [9:0] eg_pure
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);
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reg [ 3:0] dr_sum;
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reg [ 9:0] dr_adj;
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reg [10:0] dr_result;
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always @(*) begin : dr_calculation
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case( rate[5:2] )
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4'b1100: dr_sum = { 2'b0, step, ~step }; // 12
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4'b1101: dr_sum = { 1'b0, step, ~step, 1'b0 }; // 13
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4'b1110: dr_sum = { step, ~step, 2'b0 }; // 14
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4'b1111: dr_sum = 4'd8;// 15
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default: dr_sum = { 2'b0, step, 1'b0 };
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endcase
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// Decay rate attenuation is multiplied by 4 for SSG operation
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dr_adj = ssg_en ? {4'd0, dr_sum, 2'd0} : {6'd0, dr_sum};
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dr_result = dr_adj + eg_in;
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end
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reg [ 7:0] ar_sum0;
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reg [ 8:0] ar_sum1;
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reg [10:0] ar_result;
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reg [ 9:0] ar_sum;
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always @(*) begin : ar_calculation
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casez( rate[5:2] )
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default: ar_sum0 = {2'd0, eg_in[9:4]};
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4'b1101: ar_sum0 = {1'd0, eg_in[9:3]};
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4'b111?: ar_sum0 = eg_in[9:2];
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endcase
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ar_sum1 = ar_sum0+9'd1;
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if( rate[5:4] == 2'b11 )
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ar_sum = step ? { ar_sum1, 1'b0 } : { 1'b0, ar_sum1 };
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else
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ar_sum = step ? { 1'b0, ar_sum1 } : 10'd0;
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ar_result = eg_in-ar_sum;
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end
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///////////////////////////////////////////////////////////
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// rate not used below this point
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reg [9:0] eg_pre_fastar; // pre fast attack rate
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always @(*) begin
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if(sum_up) begin
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if( attack )
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eg_pre_fastar = ar_result[10] ? 10'd0: ar_result[9:0];
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else
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eg_pre_fastar = dr_result[10] ? 10'h3FF : dr_result[9:0];
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end
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else eg_pre_fastar = eg_in;
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eg_pure = (attack&rate[5:1]==5'h1F) ? 10'd0 : eg_pre_fastar;
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end
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endmodule // jt12_eg_pure
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