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57 lines
1.6 KiB
Verilog
57 lines
1.6 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 29-10-2018
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*/
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module jt12_eg_final(
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input [ 6:0] lfo_mod,
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input amsen,
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input [ 1:0] ams,
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input [ 6:0] tl,
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input [ 9:0] eg_pure_in,
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input ssg_inv,
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output reg [9:0] eg_limited
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);
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reg [ 8:0] am_final;
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reg [11:0] sum_eg_tl;
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reg [11:0] sum_eg_tl_am;
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reg [ 5:0] am_inverted;
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reg [ 9:0] eg_pream;
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always @(*) begin
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am_inverted = lfo_mod[6] ? ~lfo_mod[5:0] : lfo_mod[5:0];
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end
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always @(*) begin
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casez( {amsen, ams } )
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default: am_final = 9'd0;
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3'b1_01: am_final = { 5'd0, am_inverted[5:2] };
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3'b1_10: am_final = { 3'd0, am_inverted };
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3'b1_11: am_final = { 2'd0, am_inverted, 1'b0 };
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endcase
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eg_pream = ssg_inv ? (10'h200-eg_pure_in) : eg_pure_in;
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sum_eg_tl = { 1'b0, tl, 3'd0 } + {1'b0, eg_pream}; // leading zeros needed to compute correctly
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sum_eg_tl_am = sum_eg_tl + { 3'd0, am_final };
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end
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always @(*)
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eg_limited = sum_eg_tl_am[11:10]==2'd0 ? sum_eg_tl_am[9:0] : 10'h3ff;
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endmodule // jt12_eg_final
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