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86 lines
1.8 KiB
Verilog
86 lines
1.8 KiB
Verilog
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// Decoding and strobing of z80 signals
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module zsignals
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(
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// clocks
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input wire clk,
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// z80 interface input
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input wire iorq_n,
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input wire mreq_n,
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input wire m1_n,
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input wire rfsh_n,
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input wire rd_n,
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input wire wr_n,
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// Z80 signals
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output wire m1,
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output wire rfsh,
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output wire rd,
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output wire wr,
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output wire iorq,
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output wire mreq,
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output wire rdwr,
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output wire iord,
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output wire iowr,
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output wire iorw,
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output wire memrd,
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output wire memwr,
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output wire memrw,
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output wire opfetch,
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output wire intack,
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// Z80 signals strobes, at fclk
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output wire iorq_s,
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output wire mreq_s,
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output wire iord_s,
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output wire iowr_s,
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output wire iorw_s,
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output wire memrd_s,
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output wire memwr_s,
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output wire memrw_s,
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output wire opfetch_s
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);
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// invertors
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assign m1 = !m1_n;
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assign rfsh = !rfsh_n;
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assign rd = !rd_n;
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assign wr = !wr_n;
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// requests
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assign iorq = !iorq_n && m1_n; // this is masked by ~M1 to avoid port decoding on INT ack
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assign mreq = !mreq_n && rfsh_n; // this is masked by ~RFSH to ignore refresh cycles as memory requests
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// combined
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assign rdwr = rd || wr;
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assign iord = iorq && rd;
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assign iowr = iorq && wr;
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assign iorw = iorq && rdwr;
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assign memrd = mreq && rd;
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assign memwr = mreq && !rd;
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assign memrw = mreq && rdwr;
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assign opfetch = memrd && m1;
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assign intack = !iorq_n && m1; // NOT masked by M1
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// strobed
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assign iorq_s = iorq_r[0] && !iorq_r[1];
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assign mreq_s = mreq_r[0] && !mreq_r[1];
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assign iord_s = iorq_s && rd;
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assign iowr_s = iorq_s && wr;
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assign iorw_s = iorq_s && rdwr;
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assign memrd_s = mreq_s && rd;
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assign memwr_s = mreq_s && !rd;
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assign memrw_s = mreq_s && rdwr;
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assign opfetch_s = memrd_s && m1;
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// latch inputs on FPGA clock
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reg [1:0] iorq_r, mreq_r;
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always @(posedge clk) begin
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iorq_r <= {iorq_r[0], iorq};
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mreq_r <= {mreq_r[0], mreq};
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end
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endmodule
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