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57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 1-31-2017
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*/
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`timescale 1ns / 1ps
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// stages must be greater than 2
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module jt12_sh_rst #(parameter width=5, stages=32, rstval=1'b0 )
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(
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input rst,
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input clk,
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input clk_en,
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input [width-1:0] din,
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output [width-1:0] drop
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);
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reg [stages-1:0] bits[width-1:0];
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genvar i;
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integer k;
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generate
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initial
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for (k=0; k < width; k=k+1) begin
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bits[k] = { stages{rstval}};
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end
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endgenerate
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generate
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for (i=0; i < width; i=i+1) begin: bit_shifter
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always @(posedge clk)
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if( rst ) begin
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bits[i] <= {stages{rstval}};
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end else if(clk_en) begin
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bits[i] <= {bits[i][stages-2:0], din[i]};
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end
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assign drop[i] = bits[i][stages-1];
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end
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endgenerate
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endmodule
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