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139 lines
4.0 KiB
Verilog
139 lines
4.0 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 30-10-2018
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*/
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module jt12_eg_comb(
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input keyon_now,
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input keyoff_now,
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input [2:0] state_in,
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input [9:0] eg_in,
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// envelope configuration
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input [4:0] arate, // attack rate
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input [4:0] rate1, // decay rate
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input [4:0] rate2, // sustain rate
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input [3:0] rrate,
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input [3:0] sl, // sustain level
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// SSG operation
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input ssg_en,
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input [2:0] ssg_eg,
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// SSG output inversion
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input ssg_inv_in,
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output ssg_inv_out,
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output [4:0] base_rate,
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output [2:0] state_next,
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output pg_rst,
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///////////////////////////////////
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// II
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input step_attack,
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input [ 4:0] step_rate_in,
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input [ 4:0] keycode,
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input [14:0] eg_cnt,
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input cnt_in,
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input [ 1:0] ks,
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output cnt_lsb,
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output step,
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output [5:0] step_rate_out,
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output sum_up_out,
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///////////////////////////////////
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// III
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input pure_attack,
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input pure_step,
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input [ 5:1] pure_rate,
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input pure_ssg_en,
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input [ 9:0] pure_eg_in,
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output [9:0] pure_eg_out,
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input sum_up_in,
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///////////////////////////////////
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// IV
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input [ 6:0] lfo_mod,
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input amsen,
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input [ 1:0] ams,
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input [ 6:0] tl,
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input [ 9:0] final_eg_in,
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input final_ssg_inv,
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output [9:0] final_eg_out
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);
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// I
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jt12_eg_ctrl u_ctrl(
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.keyon_now ( keyon_now ),
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.keyoff_now ( keyoff_now ),
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.state_in ( state_in ),
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.eg ( eg_in ),
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// envelope configuration
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.arate ( arate ), // attack rate
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.rate1 ( rate1 ), // decay rate
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.rate2 ( rate2 ), // sustain rate
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.rrate ( rrate ),
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.sl ( sl ), // sustain level
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// SSG operation
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.ssg_en ( ssg_en ),
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.ssg_eg ( ssg_eg ),
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// SSG output inversion
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.ssg_inv_in ( ssg_inv_in ),
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.ssg_inv_out ( ssg_inv_out ),
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.base_rate ( base_rate ),
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.state_next ( state_next ),
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.pg_rst ( pg_rst )
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);
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// II
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jt12_eg_step u_step(
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.attack ( step_attack ),
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.base_rate ( step_rate_in ),
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.keycode ( keycode ),
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.eg_cnt ( eg_cnt ),
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.cnt_in ( cnt_in ),
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.ks ( ks ),
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.cnt_lsb ( cnt_lsb ),
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.step ( step ),
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.rate ( step_rate_out ),
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.sum_up ( sum_up_out )
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);
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// III
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wire [9:0] egin, egout;
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jt12_eg_pure u_pure(
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.attack ( pure_attack ),
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.step ( pure_step ),
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.rate ( pure_rate ),
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.ssg_en ( pure_ssg_en ),
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.eg_in ( pure_eg_in ),
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.eg_pure( pure_eg_out ),
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.sum_up ( sum_up_in )
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);
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// IV
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jt12_eg_final u_final(
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.lfo_mod ( lfo_mod ),
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.amsen ( amsen ),
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.ams ( ams ),
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.tl ( tl ),
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.ssg_inv ( final_ssg_inv ),
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.eg_pure_in ( final_eg_in ),
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.eg_limited ( final_eg_out )
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);
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endmodule // jt12_eg_comb
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