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83 lines
2.2 KiB
Verilog
83 lines
2.2 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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`timescale 1ns / 1ps
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module jt12_div(
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input rst,
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input clk,
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input cen,
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input [1:0] div_setting,
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output reg clk_en,
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output reg clk_en_ssg
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);
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parameter use_ssg=0, num_ch;
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reg [3:0] opn_pres, opn_cnt;
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reg [2:0] ssg_pres, ssg_cnt;
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reg cen_int, cen_ssg_int;
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always @(*)
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if( num_ch==6 ) begin
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opn_pres = 4'd5;
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ssg_pres = 3'd3; // unused, really
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end
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else
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casez( div_setting )
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2'b0?: { opn_pres, ssg_pres } = { 4'd2-4'd1, 3'd0 }; // 2
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2'b10: { opn_pres, ssg_pres } = { 4'd6-4'd1, 3'd3 }; // 6 - Default for YM2608
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2'b11: { opn_pres, ssg_pres } = { 4'd3-4'd1, 3'd1 }; // 3 - Default for YM2203
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endcase // div_setting
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always @(negedge clk) begin
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cen_int <= opn_cnt == 4'd0;
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cen_ssg_int <= ssg_cnt == 3'd0;
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`ifdef FASTDIV
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// always enabled for fast sims (use with GYM output, timer will not work well)
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clk_en <= 1'b1;
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clk_en_ssg <= 1'b1;
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`else
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clk_en <= cen & cen_int;
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clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
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`endif
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end
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// OPN
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always @(posedge clk)
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if( cen ) begin
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if( opn_cnt == opn_pres ) begin
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opn_cnt <= 4'd0;
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end
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else opn_cnt <= opn_cnt + 4'd1;
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end
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// SSG
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always @(posedge clk)
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if( cen ) begin
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if( ssg_cnt == ssg_pres ) begin
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ssg_cnt <= 3'd0;
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end
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else ssg_cnt <= ssg_cnt + 3'd1;
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end
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endmodule // jt12_div
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