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82 lines
2.8 KiB
Verilog
82 lines
2.8 KiB
Verilog
/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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module jt12_csr( // Circular Shift Register + input mux
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input rst,
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input clk,
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input clk_en,
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input [ 7:0] din,
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input [43:0] shift_in,
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output [43:0] shift_out,
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input up_tl,
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input up_dt1,
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input up_ks_ar,
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input up_amen_dr,
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input up_sr,
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input up_sl_rr,
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input up_ssgeg,
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input update_op_I,
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input update_op_II,
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input update_op_IV
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);
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localparam regop_width=44;
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reg [regop_width-1:0] regop_in;
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jt12_sh_rst #(.width(regop_width),.stages(12)) u_regch(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.rst ( rst ),
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.din ( regop_in ),
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.drop ( shift_out )
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);
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wire up_tl_op = up_tl & update_op_IV;
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wire up_dt1_op = up_dt1 & update_op_I;
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wire up_mul_op = up_dt1 & update_op_II;
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wire up_ks_op = up_ks_ar & update_op_II;
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wire up_ar_op = up_ks_ar & update_op_I;
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wire up_amen_op = up_amen_dr& update_op_IV;
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wire up_dr_op = up_amen_dr& update_op_I;
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wire up_sr_op = up_sr & update_op_I;
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wire up_sl_op = up_sl_rr & update_op_I;
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wire up_rr_op = up_sl_rr & update_op_I;
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wire up_ssg_op = up_ssgeg & update_op_I;
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always @(*)
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regop_in = {
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up_tl_op ? din[6:0] : shift_in[43:37], // 7
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up_dt1_op ? din[6:4] : shift_in[36:34], // 3
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up_mul_op ? din[3:0] : shift_in[33:30], // 4
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up_ks_op ? din[7:6] : shift_in[29:28], // 2
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up_ar_op ? din[4:0] : shift_in[27:23], // 5
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up_amen_op ? din[7] : shift_in[ 22], // 1
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up_dr_op ? din[4:0] : shift_in[21:17], // 5
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up_sr_op ? din[4:0] : shift_in[16:12], // 5
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up_sl_op ? din[7:4] : shift_in[11: 8], // 4
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up_rr_op ? din[3:0] : shift_in[ 7: 4], // 4
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up_ssg_op ? din[3:0] : shift_in[ 3: 0] // 4
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};
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endmodule // jt12_reg
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