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53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
/* This file is part of JT49.
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JT49 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT49 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT49. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-Nov-2018
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Based on sqmusic, by the same author
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*/
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module jt49_div #(parameter W=12 )(
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(* direct_enable *) input cen,
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input clk, // this is the divided down clock from the core
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input rst_n,
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input [W-1:0] period,
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output reg div
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);
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reg [W-1:0]count;
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wire [W-1:0] one = { {W-1{1'b0}}, 1'b1};
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always @(posedge clk, negedge rst_n ) begin
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if( !rst_n) begin
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count <= one;
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div <= 1'b0;
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end
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else if(cen) begin
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if( count>=period ) begin
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count <= one;
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div <= ~div;
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end
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else
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/*if( period!={W{1'b0}} )*/ count <= count + one ;
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end
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end
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endmodule
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