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56 lines
1.5 KiB
Verilog
56 lines
1.5 KiB
Verilog
/* This file is part of JT49.
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JT49 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT49 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT49. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 10-Nov-2018
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Based on sqmusic, by the same author
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*/
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module jt49_cen(
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input clk,
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input rst_n,
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input cen, // base clock enable signal
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input sel, // when low, divide by 2 once more
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output reg cen16,
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output reg cen256
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);
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reg [9:0] cencnt;
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parameter CLKDIV = 3; // use 3 for standalone JT49 or 2
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localparam eg = CLKDIV; //8;
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wire toggle16 = sel ? ~|cencnt[CLKDIV-1:0] : ~|cencnt[CLKDIV:0];
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wire toggle256= sel ? ~|cencnt[eg-2:0] : ~|cencnt[eg-1:0];
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always @(posedge clk, negedge rst_n) begin
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if(!rst_n)
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cencnt <= 10'd0;
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else begin
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if(cen) cencnt <= cencnt+10'd1;
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end
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end
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always @(posedge clk) begin
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cen16 <= cen & toggle16;
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cen256 <= cen & toggle256;
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end
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endmodule // jt49_cen
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