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105 lines
3.2 KiB
Verilog
105 lines
3.2 KiB
Verilog
/* This file is part of JT49.
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JT49 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT49 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT49. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 28-Jan-2019
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Based on sqmusic, by the same author
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*/
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// This is a wrapper with the BDIR/BC1 pins
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module jt49_bus ( // note that input ports are not multiplexed
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input rst_n,
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input clk, // signal on positive edge
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input clk_en /* synthesis direct_enable = 1 */,
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// bus control pins of original chip
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input bdir,
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input bc1,
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input [7:0] din,
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input sel, // if sel is low, the clock is divided by 2
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output [7:0] dout,
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output [9:0] sound, // combined channel output
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output [7:0] A, // linearised channel output
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output [7:0] B,
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output [7:0] C,
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output sample,
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input [7:0] IOA_in,
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output [7:0] IOA_out,
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output IOA_oe,
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input [7:0] IOB_in,
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output [7:0] IOB_out,
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output IOB_oe
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);
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parameter [2:0] COMP=3'b000;
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reg wr_n, cs_n;
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reg [3:0] addr;
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reg addr_ok;
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reg [7:0] din_latch;
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always @(posedge clk)
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if( !rst_n ) begin
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wr_n <= 1'b1;
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cs_n <= 1'b1;
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addr <= 4'd0;
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addr_ok <= 1'b1;
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end else begin // I/O cannot use clk_en
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// addr must be
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case( {bdir,bc1} )
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2'b00: { wr_n, cs_n } <= 2'b11;
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2'b01: { wr_n, cs_n } <= addr_ok ? 2'b10 : 2'b11;
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2'b10: begin
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{ wr_n, cs_n } <= addr_ok ? 2'b00 : 2'b11;
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din_latch <= din;
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end
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2'b11: begin
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{ wr_n, cs_n } <= 2'b11;
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addr <= din[3:0];
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addr_ok <= din[7:4] == 4'd0;
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end
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endcase // {bdir,bc1}
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end
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jt49 #(.COMP(COMP)) u_jt49( // note that input ports are not multiplexed
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.rst_n ( rst_n ),
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.clk ( clk ), // signal on positive edge
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.clk_en ( clk_en ), // clock enable on negative edge
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.addr ( addr[3:0] ),
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.cs_n ( cs_n ),
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.wr_n ( wr_n ), // write
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.din ( din_latch ),
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.sel ( sel ), // if sel is low, the clock is divided by 2
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.dout ( dout ),
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.sound ( sound ), // combined channel output
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.sample ( sample ),
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.A ( A ), // linearised channel output
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.B ( B ),
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.C ( C ),
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.IOA_in ( IOA_in ),
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.IOA_out( IOA_out ),
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.IOA_oe ( IOA_oe ),
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.IOB_in ( IOB_in ),
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.IOB_out( IOB_out ),
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.IOB_oe ( IOB_oe )
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);
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endmodule // jt49_bus
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