mirror of
https://github.com/UzixLS/TSConf_MiST.git
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698 lines
22 KiB
Verilog
698 lines
22 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2016
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Based on information posted by Nemesis on:
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http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
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Based on jt51_phasegen.v, from JT51
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*/
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module jt12_top (
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input rst, // rst should be at least 6 clk&cen cycles long
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input clk, // CPU clock
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(* direct_enable *) input cen, // optional clock enable, if not needed leave as 1'b1
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input [7:0] din,
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input [1:0] addr,
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input cs_n,
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input wr_n,
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output [7:0] dout,
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output irq_n,
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// Configuration
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input en_hifi_pcm, // high to enable PCM interpolation on YM2612 mode
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// ADPCM pins
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output [19:0] adpcma_addr, // real hardware has 10 pins multiplexed through RMPX pin
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output [ 3:0] adpcma_bank,
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output adpcma_roe_n, // ADPCM-A ROM output enable
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input [ 7:0] adpcma_data, // Data from RAM
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output [23:0] adpcmb_addr, // real hardware has 12 pins multiplexed through PMPX pin
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input [ 7:0] adpcmb_data,
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output adpcmb_roe_n, // ADPCM-B ROM output enable
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// I/O pins used by YM2203 embedded YM2149 chip
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input [7:0] IOA_in,
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input [7:0] IOB_in,
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output [7:0] IOA_out,
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output [7:0] IOB_out,
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output IOA_oe,
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output IOB_oe,
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// Separated output
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output [ 7:0] psg_A,
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output [ 7:0] psg_B,
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output [ 7:0] psg_C,
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output signed [15:0] fm_snd_left,
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output signed [15:0] fm_snd_right,
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output signed [15:0] adpcmA_l,
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output signed [15:0] adpcmA_r,
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output signed [15:0] adpcmB_l,
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output signed [15:0] adpcmB_r,
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// combined output
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output [ 9:0] psg_snd,
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output signed [15:0] snd_right, // FM+PSG
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output signed [15:0] snd_left, // FM+PSG
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output snd_sample,
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input [ 5:0] ch_enable, // ADPCM-A channels
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input [ 7:0] debug_bus,
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output [ 7:0] debug_view
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);
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// parameters to select the features for each chip type
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// defaults to YM2612
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parameter use_lfo=1, use_ssg=0, num_ch=6, use_pcm=1;
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parameter use_adpcm=0;
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parameter JT49_DIV=2,
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YM2203_LUMPED=0;
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parameter mask_div=1;
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wire flag_A, flag_B, busy;
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wire write = !cs_n && !wr_n;
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wire clk_en, clk_en_ssg;
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// Timers
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wire [9:0] value_A;
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wire [7:0] value_B;
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wire load_A, load_B;
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wire enable_irq_A, enable_irq_B;
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wire clr_flag_A, clr_flag_B;
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wire overflow_A;
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wire fast_timers;
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wire zero; // Single-clock pulse at the begginig of s1_enters
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// LFO
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wire [2:0] lfo_freq;
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wire lfo_en;
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// Operators
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wire amsen_IV;
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wire [ 2:0] dt1_I;
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wire [ 3:0] mul_II;
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wire [ 6:0] tl_IV;
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wire [ 4:0] keycode_II;
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wire [ 4:0] ar_I;
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wire [ 4:0] d1r_I;
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wire [ 4:0] d2r_I;
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wire [ 3:0] rr_I;
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wire [ 3:0] sl_I;
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wire [ 1:0] ks_II;
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// SSG operation
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wire ssg_en_I;
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wire [2:0] ssg_eg_I;
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// envelope operation
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wire keyon_I;
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wire [9:0] eg_IX;
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wire pg_rst_II;
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// Channel
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wire [10:0] fnum_I;
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wire [ 2:0] block_I;
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wire [ 1:0] rl;
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wire [ 2:0] fb_II;
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wire [ 2:0] alg_I;
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wire [ 2:0] pms_I;
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wire [ 1:0] ams_IV;
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// PCM
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wire pcm_en, pcm_wr;
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wire [ 8:0] pcm;
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// Test
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wire pg_stop, eg_stop;
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wire ch6op;
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wire [ 2:0] cur_ch;
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wire [ 1:0] cur_op;
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// Operator
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wire xuse_internal, yuse_internal;
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wire xuse_prevprev1, xuse_prev2, yuse_prev1, yuse_prev2;
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wire [ 9:0] phase_VIII;
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wire s1_enters, s2_enters, s3_enters, s4_enters;
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wire rst_int;
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// LFO
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wire [6:0] lfo_mod;
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wire lfo_rst;
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// PSG
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wire [3:0] psg_addr;
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wire [7:0] psg_data, psg_dout;
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wire psg_wr_n;
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// ADPCM-A
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wire [15:0] addr_a;
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wire [ 2:0] up_addr, up_lracl;
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wire up_start, up_end;
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wire [ 7:0] aon_a, lracl;
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wire [ 5:0] atl_a; // ADPCM Total Level
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wire up_aon;
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// APDCM-B
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wire acmd_on_b; // Control - Process start, Key On
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wire acmd_rep_b; // Control - Repeat
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wire acmd_rst_b; // Control - Reset
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wire acmd_up_b; // Control - New cmd received
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wire [ 1:0] alr_b; // Left / Right
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wire [15:0] astart_b; // Start address
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wire [15:0] aend_b; // End address
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wire [15:0] adeltan_b; // Delta-N
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wire [ 7:0] aeg_b; // Envelope Generator Control
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wire [ 5:0] adpcma_flags; // ADPMC-A read over flags
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wire adpcmb_flag;
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wire [ 6:0] flag_ctl;
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wire [ 6:0] flag_mask;
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wire [ 1:0] div_setting;
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wire clk_en_2, clk_en_666, clk_en_111, clk_en_55;
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assign debug_view = { 4'd0, flag_B, flag_A, div_setting };
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generate
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if( use_adpcm==1 ) begin: gen_adpcm
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wire rst_n;
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jt12_rst u_rst(
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.rst ( rst ),
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.clk ( clk ),
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.rst_n ( rst_n )
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);
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jt10_adpcm_drvA u_adpcm_a(
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.rst_n ( rst_n ),
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.clk ( clk ),
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.cen ( cen ),
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.cen6 ( clk_en_666 ), // clk & cen must be 666 kHz
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.cen1 ( clk_en_111 ), // clk & cen must be 111 kHz
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.addr ( adpcma_addr ), // real hardware has 10 pins multiplexed through RMPX pin
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.bank ( adpcma_bank ),
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.roe_n ( adpcma_roe_n ), // ADPCM-A ROM output enable
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.datain ( adpcma_data ),
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// Control Registers
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.atl ( atl_a ), // ADPCM Total Level
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.addr_in ( addr_a ),
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.lracl_in ( lracl ),
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.up_start ( up_start ),
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.up_end ( up_end ),
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.up_addr ( up_addr ),
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.up_lracl ( up_lracl ),
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.aon_cmd ( aon_a ), // ADPCM ON equivalent to key on for FM
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.up_aon ( up_aon ),
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// Flags
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.flags ( adpcma_flags ),
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.clr_flags ( flag_ctl[5:0] ),
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.pcm55_l ( adpcmA_l ),
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.pcm55_r ( adpcmA_r ),
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.ch_enable ( ch_enable )
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);
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jt10_adpcm_drvB u_adpcm_b(
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.rst_n ( rst_n ),
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.clk ( clk ),
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.cen ( cen ),
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.cen55 ( clk_en_55 ),
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// Control
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.acmd_on_b ( acmd_on_b ), // Control - Process start, Key On
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.acmd_rep_b ( acmd_rep_b ), // Control - Repeat
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.acmd_rst_b ( acmd_rst_b ), // Control - Reset
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.acmd_up_b ( acmd_up_b ), // Control - New command received
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.alr_b ( alr_b ), // Left / Right
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.astart_b ( astart_b ), // Start address
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.aend_b ( aend_b ), // End address
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.adeltan_b ( adeltan_b ), // Delta-N
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.aeg_b ( aeg_b ), // Envelope Generator Control
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// Flag
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.flag ( adpcmb_flag ),
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.clr_flag ( flag_ctl[6] ),
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// memory
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.addr ( adpcmb_addr ),
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.data ( adpcmb_data ),
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.roe_n ( adpcmb_roe_n ),
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.pcm55_l ( adpcmB_l ),
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.pcm55_r ( adpcmB_r )
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);
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assign snd_sample = zero;
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jt10_acc u_acc(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.op_result ( op_result_hd ),
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.rl ( rl ),
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.zero ( zero ),
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.s1_enters ( s2_enters ),
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.s2_enters ( s1_enters ),
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.s3_enters ( s4_enters ),
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.s4_enters ( s3_enters ),
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.cur_ch ( cur_ch ),
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.cur_op ( cur_op ),
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.alg ( alg_I ),
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.adpcmA_l ( adpcmA_l ),
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.adpcmA_r ( adpcmA_r ),
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.adpcmB_l ( adpcmB_l ),
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.adpcmB_r ( adpcmB_r ),
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// combined output
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.left ( fm_snd_left ),
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.right ( fm_snd_right )
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);
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end else begin : gen_adpcm_no
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assign adpcmA_l = 'd0;
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assign adpcmA_r = 'd0;
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assign adpcmB_l = 'd0;
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assign adpcmB_r = 'd0;
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assign adpcma_addr = 'd0;
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assign adpcma_bank = 'd0;
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assign adpcma_roe_n = 'b1;
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assign adpcmb_addr = 'd0;
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assign adpcmb_roe_n = 'd1;
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assign adpcma_flags = 0;
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assign adpcmb_flag = 0;
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end
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endgenerate
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jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
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// .rst_n ( rst_n ),
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.clk ( clk ), // CPU clock
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.flag_A ( flag_A ),
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.flag_B ( flag_B ),
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.busy ( busy ),
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.adpcma_flags ( adpcma_flags & flag_mask[5:0] ),
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.adpcmb_flag ( adpcmb_flag & flag_mask[6] ),
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.psg_dout ( psg_dout ),
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.addr ( addr ),
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.dout ( dout )
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);
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jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm), .mask_div(mask_div))
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u_mmr(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ), // external clock enable
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.clk_en ( clk_en ), // internal clock enable
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.clk_en_2 ( clk_en_2 ), // input cen divided by 2
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.clk_en_ssg ( clk_en_ssg), // internal clock enable
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.clk_en_666 ( clk_en_666),
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.clk_en_111 ( clk_en_111),
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.clk_en_55 ( clk_en_55 ),
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.din ( din ),
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.write ( write ),
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.addr ( addr ),
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.busy ( busy ),
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.ch6op ( ch6op ),
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.cur_ch ( cur_ch ),
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.cur_op ( cur_op ),
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// LFO
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.lfo_freq ( lfo_freq ),
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.lfo_en ( lfo_en ),
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// Timers
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.enable_irq_A ( enable_irq_A ),
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.enable_irq_B ( enable_irq_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.overflow_A ( overflow_A ),
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.fast_timers( fast_timers ),
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// PCM
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.pcm ( pcm ),
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.pcm_en ( pcm_en ),
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.pcm_wr ( pcm_wr ),
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// ADPCM-A
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.aon_a ( aon_a ), // ON
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.atl_a ( atl_a ), // TL
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.addr_a ( addr_a ), // address latch
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.lracl ( lracl ), // L/R ADPCM Channel Level
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.up_start ( up_start ), // write enable start address latch
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.up_end ( up_end ), // write enable end address latch
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.up_addr ( up_addr ), // write enable end address latch
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.up_lracl ( up_lracl ),
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.up_aon ( up_aon ),
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// ADPCM-B
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.acmd_on_b ( acmd_on_b ), // Control - Process start, Key On
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.acmd_rep_b ( acmd_rep_b ), // Control - Repeat
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.acmd_rst_b ( acmd_rst_b ), // Control - Reset
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.acmd_up_b ( acmd_up_b ), // Control - New command received
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.alr_b ( alr_b ), // Left / Right
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.astart_b ( astart_b ), // Start address
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.aend_b ( aend_b ), // End address
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.adeltan_b ( adeltan_b ), // Delta-N
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.aeg_b ( aeg_b ), // Envelope Generator Control
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.flag_ctl ( flag_ctl ),
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.flag_mask ( flag_mask ),
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// Operator
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.xuse_prevprev1 ( xuse_prevprev1 ),
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.xuse_internal ( xuse_internal ),
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.yuse_internal ( yuse_internal ),
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.xuse_prev2 ( xuse_prev2 ),
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.yuse_prev1 ( yuse_prev1 ),
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.yuse_prev2 ( yuse_prev2 ),
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// PG
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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.pg_stop ( pg_stop ),
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// EG
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.rl ( rl ),
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.fb_II ( fb_II ),
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.alg_I ( alg_I ),
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.pms_I ( pms_I ),
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.ams_IV ( ams_IV ),
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.amsen_IV ( amsen_IV ),
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.dt1_I ( dt1_I ),
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.mul_II ( mul_II ),
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.tl_IV ( tl_IV ),
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.ar_I ( ar_I ),
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.d1r_I ( d1r_I ),
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.d2r_I ( d2r_I ),
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.rr_I ( rr_I ),
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.sl_I ( sl_I ),
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.ks_II ( ks_II ),
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.eg_stop ( eg_stop ),
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// SSG operation
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.ssg_en_I ( ssg_en_I ),
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.ssg_eg_I ( ssg_eg_I ),
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.keyon_I ( keyon_I ),
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// Operator
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.zero ( zero ),
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.s1_enters ( s1_enters ),
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.s2_enters ( s2_enters ),
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.s3_enters ( s3_enters ),
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.s4_enters ( s4_enters ),
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// PSG interace
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.psg_addr ( psg_addr ),
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.psg_data ( psg_data ),
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.psg_wr_n ( psg_wr_n ),
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.debug_bus ( debug_bus ),
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.div_setting(div_setting)
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);
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// YM2203 seems to use a fixed cen/3 clock for the timers, regardless
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// of the prescaler setting
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wire timer_cen = fast_timers ? cen : clk_en;
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jt12_timers #(.num_ch(num_ch)) u_timers (
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.clk ( clk ),
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.clk_en ( timer_cen ),
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.rst ( rst ),
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.zero ( zero ),
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.enable_irq_A( enable_irq_A ),
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.enable_irq_B( enable_irq_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.flag_B ( flag_B ),
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.overflow_A ( overflow_A ),
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.irq_n ( irq_n )
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);
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// YM2203 does not have LFO
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generate
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if( use_lfo== 1) begin : gen_lfo
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jt12_lfo u_lfo(
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.rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.zero ( zero ),
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`ifdef NOLFO
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.lfo_rst ( 1'b1 ),
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`else
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.lfo_rst ( 1'b0 ),
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`endif
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.lfo_en ( lfo_en ),
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.lfo_freq ( lfo_freq ),
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.lfo_mod ( lfo_mod )
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);
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end else begin : gen_nolfo
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assign lfo_mod = 7'd0;
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end
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endgenerate
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// YM2203/YM2610 have a PSG
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`ifndef NOSSG
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generate
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if( use_ssg==1 ) begin : gen_ssg
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jt49 #(.COMP(3'b01), .CLKDIV(JT49_DIV), .YM2203_LUMPED(YM2203_LUMPED))
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u_psg( // note that input ports are not multiplexed
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.rst_n ( ~rst ),
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.clk ( clk ), // signal on positive edge
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.clk_en ( clk_en_ssg), // clock enable on negative edge
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.addr ( psg_addr ),
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.cs_n ( 1'b0 ),
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|
.wr_n ( psg_wr_n ), // write
|
|
.din ( psg_data ),
|
|
.sound ( psg_snd ), // combined output
|
|
.A ( psg_A ),
|
|
.B ( psg_B ),
|
|
.C ( psg_C ),
|
|
.dout ( psg_dout ),
|
|
.sel ( 1'b1 ), // half clock speed
|
|
.IOA_out ( IOA_out ),
|
|
.IOB_out ( IOB_out ),
|
|
.IOA_in ( IOA_in ),
|
|
.IOB_in ( IOB_in ),
|
|
.IOA_oe ( IOA_oe ),
|
|
.IOB_oe ( IOB_oe ),
|
|
// Unused:
|
|
.sample ( )
|
|
);
|
|
assign snd_left = fm_snd_left + { 1'b0, psg_snd[9:0],5'd0};
|
|
assign snd_right = fm_snd_right + { 1'b0, psg_snd[9:0],5'd0};
|
|
end else begin : gen_nossg
|
|
assign psg_snd = 10'd0;
|
|
assign snd_left = fm_snd_left;
|
|
assign snd_right= fm_snd_right;
|
|
assign psg_dout = 8'd0;
|
|
assign psg_A = 8'd0;
|
|
assign psg_B = 8'd0;
|
|
assign psg_C = 8'd0;
|
|
assign IOA_oe = 0;
|
|
assign IOB_oe = 0;
|
|
assign IOA_out = 0;
|
|
assign IOB_out = 0;
|
|
end
|
|
endgenerate
|
|
`else
|
|
assign psg_snd = 10'd0;
|
|
assign snd_left = fm_snd_left;
|
|
assign snd_right= fm_snd_right;
|
|
assign psg_dout = 8'd0;
|
|
`endif
|
|
|
|
wire [ 8:0] op_result;
|
|
wire [13:0] op_result_hd;
|
|
`ifndef NOFM
|
|
|
|
jt12_pg #(.num_ch(num_ch)) u_pg(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
// Channel frequency
|
|
.fnum_I ( fnum_I ),
|
|
.block_I ( block_I ),
|
|
// Operator multiplying
|
|
.mul_II ( mul_II ),
|
|
// Operator detuning
|
|
.dt1_I ( dt1_I ), // same as JT51's DT1
|
|
// Phase modulation by LFO
|
|
.lfo_mod ( lfo_mod ),
|
|
.pms_I ( pms_I ),
|
|
// phase operation
|
|
.pg_rst_II ( pg_rst_II ),
|
|
.pg_stop ( pg_stop ),
|
|
.keycode_II ( keycode_II ),
|
|
.phase_VIII ( phase_VIII )
|
|
);
|
|
|
|
wire [9:0] eg_V;
|
|
|
|
jt12_eg #(.num_ch(num_ch)) u_eg(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.zero ( zero ),
|
|
.eg_stop ( eg_stop ),
|
|
// envelope configuration
|
|
.keycode_II ( keycode_II ),
|
|
.arate_I ( ar_I ), // attack rate
|
|
.rate1_I ( d1r_I ), // decay rate
|
|
.rate2_I ( d2r_I ), // sustain rate
|
|
.rrate_I ( rr_I ), // release rate
|
|
.sl_I ( sl_I ), // sustain level
|
|
.ks_II ( ks_II ), // key scale
|
|
// SSG operation
|
|
.ssg_en_I ( ssg_en_I ),
|
|
.ssg_eg_I ( ssg_eg_I ),
|
|
// envelope operation
|
|
.keyon_I ( keyon_I ),
|
|
// envelope number
|
|
.lfo_mod ( lfo_mod ),
|
|
.tl_IV ( tl_IV ),
|
|
.ams_IV ( ams_IV ),
|
|
.amsen_IV ( amsen_IV ),
|
|
|
|
.eg_V ( eg_V ),
|
|
.pg_rst_II ( pg_rst_II )
|
|
);
|
|
|
|
jt12_sh #(.width(10),.stages(4)) u_egpad(
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.din ( eg_V ),
|
|
.drop ( eg_IX )
|
|
);
|
|
|
|
jt12_op #(.num_ch(num_ch)) u_op(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.pg_phase_VIII ( phase_VIII ),
|
|
.eg_atten_IX ( eg_IX ),
|
|
.fb_II ( fb_II ),
|
|
|
|
.test_214 ( 1'b0 ),
|
|
.s1_enters ( s1_enters ),
|
|
.s2_enters ( s2_enters ),
|
|
.s3_enters ( s3_enters ),
|
|
.s4_enters ( s4_enters ),
|
|
.xuse_prevprev1 ( xuse_prevprev1),
|
|
.xuse_internal ( xuse_internal ),
|
|
.yuse_internal ( yuse_internal ),
|
|
.xuse_prev2 ( xuse_prev2 ),
|
|
.yuse_prev1 ( yuse_prev1 ),
|
|
.yuse_prev2 ( yuse_prev2 ),
|
|
.zero ( zero ),
|
|
.op_result ( op_result ),
|
|
.full_result ( op_result_hd )
|
|
);
|
|
`else
|
|
assign op_result = 'd0;
|
|
assign op_result_hd = 'd0;
|
|
`endif
|
|
|
|
generate
|
|
if( use_pcm==1 ) begin: gen_pcm_acc // YM2612 accumulator
|
|
assign fm_snd_right[3:0] = 4'd0;
|
|
assign fm_snd_left [3:0] = 4'd0;
|
|
assign snd_sample = zero;
|
|
reg signed [8:0] pcm2;
|
|
|
|
// interpolate PCM samples with automatic sample rate detection
|
|
// this feature is not present in original YM2612
|
|
// this improves PCM sample sound greatly
|
|
/*
|
|
jt12_pcm u_pcm(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.zero ( zero ),
|
|
.pcm ( pcm ),
|
|
.pcm_wr ( pcm_wr ),
|
|
.pcm_resampled ( pcm2 )
|
|
);
|
|
*/
|
|
wire rst_pcm_n;
|
|
|
|
jt12_rst u_rst_pcm(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.rst_n ( rst_pcm_n )
|
|
);
|
|
|
|
`ifndef NOPCMLINEAR
|
|
wire signed [10:0] pcm_full;
|
|
always @(*)
|
|
pcm2 = en_hifi_pcm ? pcm_full[9:1] : pcm;
|
|
|
|
jt12_pcm_interpol #(.DW(11), .stepw(5)) u_pcm (
|
|
.rst_n ( rst_pcm_n ),
|
|
.clk ( clk ),
|
|
.cen ( clk_en ),
|
|
.cen55 ( clk_en_55 ),
|
|
.pcm_wr( pcm_wr ),
|
|
.pcmin ( {pcm[8],pcm, 1'b0} ),
|
|
.pcmout( pcm_full )
|
|
);
|
|
`else
|
|
assign pcm2 = pcm;
|
|
`endif
|
|
|
|
jt12_acc u_acc(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.op_result ( op_result ),
|
|
.rl ( rl ),
|
|
// note that the order changes to deal
|
|
// with the operator pipeline delay
|
|
.zero ( zero ),
|
|
.s1_enters ( s2_enters ),
|
|
.s2_enters ( s1_enters ),
|
|
.s3_enters ( s4_enters ),
|
|
.s4_enters ( s3_enters ),
|
|
.ch6op ( ch6op ),
|
|
.pcm_en ( pcm_en ), // only enabled for channel 6
|
|
.pcm ( pcm2 ),
|
|
.alg ( alg_I ),
|
|
// combined output
|
|
.left ( fm_snd_left [15:4] ),
|
|
.right ( fm_snd_right[15:4] )
|
|
);
|
|
end
|
|
if( use_pcm==0 && use_adpcm==0 ) begin : gen_2203_acc // YM2203 accumulator
|
|
wire signed [15:0] mono_snd;
|
|
assign fm_snd_left = mono_snd;
|
|
assign fm_snd_right = mono_snd;
|
|
assign snd_sample = zero;
|
|
jt03_acc u_acc(
|
|
.rst ( rst ),
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.op_result ( op_result_hd ),
|
|
// note that the order changes to deal
|
|
// with the operator pipeline delay
|
|
.s1_enters ( s1_enters ),
|
|
.s2_enters ( s2_enters ),
|
|
.s3_enters ( s3_enters ),
|
|
.s4_enters ( s4_enters ),
|
|
.alg ( alg_I ),
|
|
.zero ( zero ),
|
|
// combined output
|
|
.snd ( mono_snd )
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
`ifdef SIMULATION
|
|
integer fsnd;
|
|
initial begin
|
|
fsnd=$fopen("jt12.raw","wb");
|
|
end
|
|
|
|
always @(posedge zero) begin
|
|
$fwrite(fsnd,"%u", {snd_left, snd_right});
|
|
end
|
|
`endif
|
|
endmodule
|