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62 lines
1.9 KiB
Verilog
62 lines
1.9 KiB
Verilog
/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-1-2017
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*/
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// Accumulates an arbitrary number of inputs with saturation
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// restart the sum when input "zero" is high
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module jt12_single_acc #(parameter
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win=14, // input data width
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wout=16 // output data width
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)(
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input clk,
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input clk_en /* synthesis direct_enable */,
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input [win-1:0] op_result,
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input sum_en,
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input zero,
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output reg [wout-1:0] snd
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);
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// for full resolution use win=14, wout=16
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// for cut down resolution use win=9, wout=12
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// wout-win should be > 0
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reg signed [wout-1:0] next, acc, current;
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reg overflow;
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wire [wout-1:0] plus_inf = { 1'b0, {(wout-1){1'b1}} }; // maximum positive value
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wire [wout-1:0] minus_inf = { 1'b1, {(wout-1){1'b0}} }; // minimum negative value
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always @(*) begin
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current = sum_en ? { {(wout-win){op_result[win-1]}}, op_result } : {wout{1'b0}};
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next = zero ? current : current + acc;
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overflow = !zero &&
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(current[wout-1] == acc[wout-1]) &&
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(acc[wout-1]!=next[wout-1]);
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end
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always @(posedge clk) if( clk_en ) begin
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acc <= overflow ? (acc[wout-1] ? minus_inf : plus_inf) : next;
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if(zero) snd <= acc;
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end
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endmodule // jt12_single_acc
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