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81 lines
1.9 KiB
Verilog
81 lines
1.9 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 1-31-2017
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*/
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module jt12_sh24 #(parameter width=5 )
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(
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input clk,
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input clk_en /* synthesis direct_enable */,
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input [width-1:0] din,
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output reg [width-1:0] st1,
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output reg [width-1:0] st2,
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output reg [width-1:0] st3,
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output reg [width-1:0] st4,
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output reg [width-1:0] st5,
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output reg [width-1:0] st6,
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output reg [width-1:0] st7,
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output reg [width-1:0] st8,
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output reg [width-1:0] st9,
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output reg [width-1:0] st10,
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output reg [width-1:0] st11,
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output reg [width-1:0] st12,
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output reg [width-1:0] st13,
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output reg [width-1:0] st14,
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output reg [width-1:0] st15,
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output reg [width-1:0] st16,
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output reg [width-1:0] st17,
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output reg [width-1:0] st18,
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output reg [width-1:0] st19,
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output reg [width-1:0] st20,
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output reg [width-1:0] st21,
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output reg [width-1:0] st22,
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output reg [width-1:0] st23,
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output reg [width-1:0] st24
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);
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always @(posedge clk) if(clk_en) begin
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st24<= st23;
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st23<= st22;
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st22<= st21;
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st21<= st20;
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st20<= st19;
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st19<= st18;
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st18<= st17;
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st17<= st16;
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st16<= st15;
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st15<= st14;
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st14<= st13;
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st13<= st12;
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st12<= st11;
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st11<= st10;
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st10<= st9;
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st9 <= st8;
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st8 <= st7;
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st7 <= st6;
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st6 <= st5;
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st5 <= st4;
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st4 <= st3;
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st3 <= st2;
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st2 <= st1;
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st1 <= din;
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end
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endmodule
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