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128 lines
3.6 KiB
Verilog
128 lines
3.6 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 23-10-2019
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*/
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// Channel data is not stored in a CSR as operators
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// Proof of that is the Splatter House arcade writes
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// channel and operator data in two consequitive accesses
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// without enough time in between to have the eight
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// channels go through the CSR. So the channel data
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// cannot be CSR, but regular registers.
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module jt12_reg_ch(
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input rst,
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input clk,
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input cen,
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input [ 7:0] din,
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input [ 2:0] up_ch,
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input [ 5:0] latch_fnum,
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input up_fnumlo,
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input up_alg,
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input up_pms,
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input [ 2:0] ch, // next active channel
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output reg [ 2:0] block,
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output reg [10:0] fnum,
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output reg [ 2:0] fb,
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output reg [ 2:0] alg,
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output reg [ 1:0] rl,
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output reg [ 1:0] ams_IV,
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output reg [ 2:0] pms
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);
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parameter NUM_CH=6;
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localparam M=NUM_CH==3?2:3;
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reg [ 2:0] reg_block[0:NUM_CH-1];
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reg [10:0] reg_fnum [0:NUM_CH-1];
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reg [ 2:0] reg_fb [0:NUM_CH-1];
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reg [ 2:0] reg_alg [0:NUM_CH-1];
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reg [ 1:0] reg_rl [0:NUM_CH-1];
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reg [ 1:0] reg_ams [0:NUM_CH-1];
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reg [ 2:0] reg_pms [0:NUM_CH-1];
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reg [ 2:0] ch_IV;
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wire [M-1:0] ch_sel, out_sel;
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function [M-1:0] chtr( input [2:0] chin );
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reg [2:0] aux;
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begin
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aux = chin[M-1] ? {1'b0,chin[1:0]}+3'd3 : // upper channels
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{1'b0,chin[1:0]}; // lower
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chtr = NUM_CH==3 ? chin[M-1:0] : aux[M-1:0];
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end
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endfunction
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assign ch_sel = chtr(up_ch);
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assign out_sel = chtr(ch);
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integer i;
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/* verilator lint_off WIDTHEXPAND */
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always @* begin
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ch_IV = ch;
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if( NUM_CH==6 )
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case(out_sel)
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0: ch_IV = 3;
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1: ch_IV = 4;
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2: ch_IV = 5;
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3: ch_IV = 0;
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4: ch_IV = 1;
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5: ch_IV = 2;
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default: ch_IV = 0;
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endcase
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end
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/* verilator lint_on WIDTHEXPAND */
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always @(posedge clk) if(cen) begin
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block <= reg_block[out_sel];
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fnum <= reg_fnum [out_sel];
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fb <= reg_fb [out_sel];
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alg <= reg_alg [out_sel];
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rl <= reg_rl [out_sel];
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ams_IV<= reg_ams [ch_IV[M-1:0]];
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pms <= reg_pms [out_sel];
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if( NUM_CH==3 ) rl <= 3; // YM2203 has no stereo output
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end
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always @(posedge clk, posedge rst) begin
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if( rst ) for(i=0;i<NUM_CH;i=i+1) begin
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reg_block[i] <= 0;
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reg_fnum [i] <= 0;
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reg_fb [i] <= 0;
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reg_alg [i] <= 0;
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reg_rl [i] <= 3;
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reg_ams [i] <= 0;
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reg_pms [i] <= 0;
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end else begin
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i = 0; // prevents latch warning in Quartus
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if( up_fnumlo ) { reg_block[ch_sel], reg_fnum[ch_sel] } <= {latch_fnum,din};
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if( up_alg ) begin
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reg_fb [ch_sel] <= din[5:3];
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reg_alg[ch_sel] <= din[2:0];
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end
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if( up_pms ) begin
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reg_rl [ch_sel] <= din[7:6];
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reg_ams[ch_sel] <= din[5:4];
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reg_pms[ch_sel] <= din[2:0];
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end
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end
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end
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endmodule |