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50 lines
1.6 KiB
Verilog
50 lines
1.6 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 2-11-2018
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Based on information posted by Nemesis on:
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http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
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Based on jt51_phasegen.v, from JT51
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*/
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module jt12_pg_inc (
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input [ 2:0] block,
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input [10:0] fnum,
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input signed [8:0] pm_offset,
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output reg [16:0] phinc_pure
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);
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reg [11:0] fnum_mod;
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always @(*) begin
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fnum_mod = {fnum,1'b0} + {{3{pm_offset[8]}},pm_offset};
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case ( block )
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3'd0: phinc_pure = { 7'd0, fnum_mod[11:2] };
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3'd1: phinc_pure = { 6'd0, fnum_mod[11:1] };
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3'd2: phinc_pure = { 5'd0, fnum_mod[11:0] };
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3'd3: phinc_pure = { 4'd0, fnum_mod, 1'd0 };
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3'd4: phinc_pure = { 3'd0, fnum_mod, 2'd0 };
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3'd5: phinc_pure = { 2'd0, fnum_mod, 3'd0 };
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3'd6: phinc_pure = { 1'd0, fnum_mod, 4'd0 };
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3'd7: phinc_pure = { fnum_mod, 5'd0 };
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endcase
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end
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endmodule // jt12_pg_inc
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