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142 lines
3.9 KiB
Verilog
142 lines
3.9 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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module jt12_div(
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input rst,
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input clk,
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input cen /* synthesis direct_enable */,
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input [1:0] div_setting,
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output reg clk_en, // after prescaler
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output reg clk_en_2, // cen divided by 2
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output reg clk_en_ssg,
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output reg clk_en_666, // 666 kHz
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output reg clk_en_111, // 111 kHz
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output reg clk_en_55 // 55 kHz
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);
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parameter use_ssg=0;
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reg [3:0] opn_pres, opn_cnt=4'd0;
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reg [2:0] ssg_pres, ssg_cnt=3'd0;
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reg [4:0] adpcm_cnt666 = 5'd0;
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reg [2:0] adpcm_cnt111 = 3'd0, adpcm_cnt55=3'd0;
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reg cen_int, cen_ssg_int, cen_adpcm_int, cen_adpcm3_int;
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// prescaler values for FM
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// reset: 1/3
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// sel1/sel2
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// 0 0 1/3
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// 0 1 1/2
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// 1 0 1/6
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// 1 1 1/2
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//
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// According to YM2608 document
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// FM SSG div[1:0]
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// reset value 1/6 1/4 10
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// 2D 1/6 1/4 10 | 10
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// 2D,2E 1/3 1/2 11 | 01
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// 2F 1/2 1/1 00 & 00
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//
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always @(*) begin
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casez( div_setting )
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2'b0?: begin // FM 1/2 - SSG 1/1
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opn_pres = 4'd2-4'd1;
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ssg_pres = 3'd0;
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end
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2'b10: begin // FM 1/6 - SSG 1/4 (reset value. Fixed for YM2610)
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opn_pres = 4'd6-4'd1;
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ssg_pres = 3'd3;
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end
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2'b11: begin // FM 1/3 - SSG 1/2
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opn_pres = 4'd3-4'd1;
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ssg_pres = 3'd1;
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end
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endcase // div_setting
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end
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`ifdef SIMULATION
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initial clk_en_666 = 1'b0;
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`endif
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reg cen_55_int;
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reg [1:0] div2=2'b0;
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always @(negedge clk) begin
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cen_int <= opn_cnt == 4'd0;
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cen_ssg_int <= ssg_cnt == 3'd0;
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cen_adpcm_int <= adpcm_cnt666 == 5'd0;
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cen_adpcm3_int <= adpcm_cnt111 == 3'd0;
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cen_55_int <= adpcm_cnt55 == 3'd0;
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`ifdef FASTDIV
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// always enabled for fast sims (use with GYM output, the timers will not work well)
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clk_en <= 1'b1;
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clk_en_2 <= 1'b1;
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clk_en_ssg <= 1'b1;
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clk_en_666 <= 1'b1;
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clk_en_55 <= 1'b1;
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`else
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clk_en <= cen & cen_int;
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clk_en_2 <= cen && (div2==2'b00);
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clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
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clk_en_666 <= cen & cen_adpcm_int;
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clk_en_111 <= cen & cen_adpcm_int & cen_adpcm3_int;
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clk_en_55 <= cen & cen_adpcm_int & cen_adpcm3_int & cen_55_int;
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`endif
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end
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// Div/2
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always @(posedge clk)
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if( cen ) begin
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div2 <= div2==2'b10 ? 2'b00 : (div2+2'b01);
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end
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// OPN
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always @(posedge clk)
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if( cen ) begin
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if( opn_cnt == opn_pres ) begin
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opn_cnt <= 4'd0;
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end
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else opn_cnt <= opn_cnt + 4'd1;
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end
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// SSG
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always @(posedge clk)
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if( cen ) begin
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if( ssg_cnt == ssg_pres ) begin
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ssg_cnt <= 3'd0;
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end
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else ssg_cnt <= ssg_cnt + 3'd1;
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end
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// ADPCM-A
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always @(posedge clk)
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if( cen ) begin
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adpcm_cnt666 <= adpcm_cnt666==5'd11 ? 5'd0 : adpcm_cnt666 + 5'd1;
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if( adpcm_cnt666==5'd0 ) begin
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adpcm_cnt111 <= adpcm_cnt111==3'd5 ? 3'd0 : adpcm_cnt111+3'd1;
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if( adpcm_cnt111==3'd0)
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adpcm_cnt55 <= adpcm_cnt55==3'd1 ? 3'd0: adpcm_cnt55+3'd1;
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end
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end
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endmodule // jt12_div
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