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107 lines
3.4 KiB
Verilog
107 lines
3.4 KiB
Verilog
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// PentEvo project (c) NedoPC 2008-2011
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//
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// Z80 clocking module, also contains some wait-stating when 14MHz
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//
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// IDEAL:
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// clk _/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zclk /```\___/```\___/```\___/```````\_______/```````\_______/```````````````\_______________/```````````````\_______________/`
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zpos `\___/```\___/```\___/```\___________/```\___________/```\___________________________/```\___________________________/```\
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________
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// clock phasing:
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// c3 must be zpos for 7mhz, therefore c1 - zneg
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// for 3.5 mhz, c3 is both zpos and zneg (alternating)
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// 14MHz rulez:
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// 1. do variable stalls for memory access.
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// 2. do fallback on 7mhz for external IO accesses
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// 3. clock switch 14-7-3.5 only at RFSH
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module zclock
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(
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input clk,
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output zclk_out,
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input c0, c2, f0, f1,
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input iorq_s,
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input external_port,
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output reg zpos,
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output reg zneg,
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// stall enables and triggers
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input cpu_stall,
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input ide_stall,
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input dos_on,
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input vdos_off,
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input [1:0] turbo // 2'b00 - 3.5 MHz
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// 2'b01 - 7.0 MHz
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// 2'b1x - 14.0 MHz
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);
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assign zclk_out = ~zclk_o;
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reg zclk_o;
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wire [1:0] turbo_int = turbo;
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// wait generator
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wire dos_io_stall = stall_start || !stall_count_end;
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wire stall_start = dos_stall || io_stall;
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wire dos_stall = dos_on || vdos_off;
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wire io_stall = iorq_s && external_port && turbo_int[1];
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wire stall_count_end = stall_count[3];
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reg [3:0] stall_count;
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always @(posedge clk) begin
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if (stall_start) begin
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if (dos_stall) stall_count <= 4; // 4 tacts 28MHz (1 tact 7MHz)
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else if (io_stall) stall_count <= 0; // 8 tacts 28MHz (1 tact 3.5MHz)
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end
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else if (!stall_count_end) stall_count <= stall_count + 3'd1;
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end
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// Z80 clocking pre-strobes
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wire pre_zpos = turbo_int[1] ? pre_zpos_140 : (turbo_int[0] ? pre_zpos_70 : pre_zpos_35);
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wire pre_zneg = turbo_int[1] ? pre_zneg_140 : (turbo_int[0] ? pre_zneg_70 : pre_zneg_35);
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wire pre_zpos_140 = f1;
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wire pre_zneg_140 = f0;
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wire pre_zpos_70 = c2;
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wire pre_zneg_70 = c0;
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wire pre_zpos_35 = c2_cnt && c2;
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wire pre_zneg_35 = !c2_cnt && c2;
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reg c2_cnt;
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always @(posedge clk) if (c2) c2_cnt <= ~c2_cnt;
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// Z80 clocking strobes
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wire stall = cpu_stall || dos_io_stall || ide_stall;
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always @(posedge clk) begin
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zpos <= !stall && pre_zpos && zclk_o;
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zneg <= !stall && pre_zneg && !zclk_o;
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end
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// make Z80 clock: account for external inversion and make some leading of clock
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// 9.5 ns propagation delay: from clk posedge to zclk returned back any edge
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// (1/28)/2=17.9ns half a clock lead
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// 2.6ns lag because of non-output register emitting of zclk_o
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// total: 5.8 ns lead of any edge of zclk relative to posedge of clk => ACCOUNT FOR THIS WHEN DOING INTER-CLOCK DATA TRANSFERS
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// Z80 clocking
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always @(negedge clk) begin
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if (zpos) zclk_o <= 0;
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if (zneg) zclk_o <= 1;
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end
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endmodule
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