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57 lines
1.1 KiB
Verilog
57 lines
1.1 KiB
Verilog
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// This module maps z80 memory accesses into FPGA RAM and ports
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module zmaps
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(
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// Z80 controls
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input wire clk,
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input wire memwr_s,
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input wire [15:0] a,
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input wire [7:0] d,
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// config data
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input wire [4:0] fmaddr,
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// FPRAM data
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output wire [15:0] zmd,
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output wire [7:0] zma,
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// DMA
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input wire [15:0] dma_data,
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input wire [7:0] dma_wraddr,
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input wire dma_cram_we,
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input wire dma_sfile_we,
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// write strobes
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output wire cram_we,
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output wire sfile_we,
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output wire regs_we
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);
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// addresses of files withing zmaps
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localparam CRAM = 3'b000;
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localparam SFYS = 3'b001;
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localparam REGS = 4'b0100;
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// control signals
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wire hit = (a[15:12] == fmaddr[3:0]) && fmaddr[4] && memwr_s;
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// write enables
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assign cram_we = dma_req ? dma_cram_we : (a[11:9] == CRAM) && a[0] && hit;
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assign sfile_we = dma_req ? dma_sfile_we : (a[11:9] == SFYS) && a[0] && hit;
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assign regs_we = (a[11:8] == REGS) && hit;
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// LSB fetching
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assign zma = dma_req ? dma_wraddr : a[8:1];
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assign zmd = dma_req ? dma_data : {d, zmd0};
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reg [7:0] zmd0;
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always @(posedge clk) if (!a[0] && hit) zmd0 <= d;
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// DMA
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wire dma_req = dma_cram_we || dma_sfile_we;
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endmodule
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